Merge branch 'feature/h4_reset_reasons' into 'master'

feat(system): updated H4 reset reasons

Closes IDF-12307

See merge request espressif/esp-idf!40499

Author: ESP-Marius

components/esp_rom/esp32h4/include/esp32h4/rom/rtc.h

@@ -85,7 +85,6 @@ typedef enum {
     POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
     RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core (hp system)*/
     DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core (hp system)*/
-    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core (hp system)*/
     TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
     TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
     RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core (hp system)*/
@@ -96,10 +95,12 @@ typedef enum {
     RTCWDT_RTC_RESET       = 16,    /**<16, RTC Watch dog reset digital core and rtc module*/
     TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
     SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
+    GLITCH_RTC_RESET       = 19,    /**<19, glitch reset*/
     EFUSE_RESET            = 20,    /**<20, efuse reset digital core (hp system)*/
     USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core (hp system)*/
     USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core (hp system)*/
     JTAG_RESET             = 24,    /**<24, jtag reset CPU*/
+    CPU_LOCKUP_RESET       = 25,    /**<25, cpu lockup reset*/
 } RESET_REASON;
 
 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
@@ -116,10 +117,12 @@ ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS
 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
 ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
 ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
+ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_CORE_PWR_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_CORE_PWR_GLITCH");
 ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
 ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
 ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
 ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
+ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU_LOCKUP");
 
 typedef enum {
     NO_SLEEP        = 0,

components/esp_system/port/soc/esp32h4/reset_reason.c

@@ -10,7 +10,6 @@
 #include "soc/rtc_periph.h"
 #include "esp32h4/rom/rtc.h"
 
-// TODO: [ESP32H4] IDF-12307 inherited from verification branch, need check
 // IDF-11910 need refactor
 
 static void esp_reset_reason_clear_hint(void);
@@ -53,10 +52,19 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
     case RESET_REASON_SYS_BROWN_OUT:
         return ESP_RST_BROWNOUT;
 
+    case RESET_REASON_CORE_PWR_GLITCH:
+        return ESP_RST_PWR_GLITCH;
+
+    case RESET_REASON_CORE_EFUSE_CRC:
+        return ESP_RST_EFUSE;
+
     case RESET_REASON_CORE_USB_UART:
     case RESET_REASON_CORE_USB_JTAG:
         return ESP_RST_USB;
 
+    case RESET_REASON_CPU_LOCKUP:
+        return ESP_RST_CPU_LOCKUP;
+
     default:
         return ESP_RST_UNKNOWN;
     }

components/soc/esp32h4/include/soc/reset_reasons.h

@@ -22,8 +22,6 @@
 extern "C" {
 #endif
 
-//TODO: [ESP32H4] IDF-12307 inherit from verify code, need check
-
 /**
  * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
  * @note refer to TRM: <Reset and Clock> chapter
@@ -43,10 +41,12 @@ typedef enum {
     RESET_REASON_SYS_RTC_WDT     = 0x10, // RTC watch dog resets digital core and rtc module
     RESET_REASON_CPU0_MWDT1      = 0x11, // Main watch dog 1 resets CPU 0
     RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
+    RESET_REASON_CORE_PWR_GLITCH = 0x13, // Glitch on power resets the digital core and rtc module
     RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core (hp system)
     RESET_REASON_CORE_USB_UART   = 0x15, // USB UART resets the digital core (hp system)
     RESET_REASON_CORE_USB_JTAG   = 0x16, // USB JTAG resets the digital core (hp system)
     RESET_REASON_CPU0_JTAG       = 0x18, // JTAG resets the CPU 0
+    RESET_REASON_CPU_LOCKUP      = 0x19, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this)
 } soc_reset_reason_t;
 
 #ifdef __cplusplus