11/*
2- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
2+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33 *
44 * SPDX-License-Identifier: Apache-2.0
55 */
@@ -193,6 +193,7 @@ extern "C" {
193193 I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) // Alias
194194/** @endcond */
195195
196+ #if SOC_I2S_HW_VERSION_1
196197/**
197198 * @brief I2S default standard clock configuration
198199 * @note Please set the mclk_multiple to I2S_MCLK_MULTIPLE_384 while using 24 bits data width
@@ -204,6 +205,20 @@ extern "C" {
204205 .clk_src = I2S_CLK_SRC_DEFAULT, \
205206 .mclk_multiple = I2S_MCLK_MULTIPLE_256, \
206207}
208+ #else
209+ /**
210+ * @brief I2S default standard clock configuration
211+ * @note Please set the mclk_multiple to I2S_MCLK_MULTIPLE_384 while using 24 bits data width
212+ * Otherwise the sample rate might be imprecise since the BCLK division is not a integer
213+ * @param rate sample rate
214+ */
215+ #define I2S_STD_CLK_DEFAULT_CONFIG (rate ) { \
216+ .sample_rate_hz = rate, \
217+ .clk_src = I2S_CLK_SRC_DEFAULT, \
218+ .mclk_multiple = I2S_MCLK_MULTIPLE_256, \
219+ .ext_clk_freq_hz = 0, \
220+ }
221+ #endif
207222
208223/**
209224 * @brief I2S slot configuration for standard mode
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