Skip to content

Commit 2bb9fb2

Browse files
committed
fix(i2s): fix uninitialize warning for the default macros
Closes #15271
1 parent c0ab63c commit 2bb9fb2

File tree

2 files changed

+17
-1
lines changed

2 files changed

+17
-1
lines changed

components/esp_driver_i2s/include/driver/i2s_std.h

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -193,6 +193,7 @@ extern "C" {
193193
I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(bits_per_sample, mono_or_stereo) // Alias
194194
/** @endcond */
195195

196+
#if SOC_I2S_HW_VERSION_1
196197
/**
197198
* @brief I2S default standard clock configuration
198199
* @note Please set the mclk_multiple to I2S_MCLK_MULTIPLE_384 while using 24 bits data width
@@ -204,6 +205,20 @@ extern "C" {
204205
.clk_src = I2S_CLK_SRC_DEFAULT, \
205206
.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
206207
}
208+
#else
209+
/**
210+
* @brief I2S default standard clock configuration
211+
* @note Please set the mclk_multiple to I2S_MCLK_MULTIPLE_384 while using 24 bits data width
212+
* Otherwise the sample rate might be imprecise since the BCLK division is not a integer
213+
* @param rate sample rate
214+
*/
215+
#define I2S_STD_CLK_DEFAULT_CONFIG(rate) { \
216+
.sample_rate_hz = rate, \
217+
.clk_src = I2S_CLK_SRC_DEFAULT, \
218+
.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
219+
.ext_clk_freq_hz = 0, \
220+
}
221+
#endif
207222

208223
/**
209224
* @brief I2S slot configuration for standard mode

components/esp_driver_i2s/include/driver/i2s_tdm.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,7 @@ extern "C" {
122122
#define I2S_TDM_CLK_DEFAULT_CONFIG(rate) { \
123123
.sample_rate_hz = rate, \
124124
.clk_src = I2S_CLK_SRC_DEFAULT, \
125+
.ext_clk_freq_hz = 0, \
125126
.mclk_multiple = I2S_MCLK_MULTIPLE_256, \
126127
.bclk_div = 8, \
127128
}

0 commit comments

Comments
 (0)