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Merge branch 'fix/fix_bad_dslp_param_after_lightsleep' into 'master'
fix(esp_hw_support): Fixed the issue that light sleep destroyed the parameters of subsequent deep sleep Closes PM-366 and BLERP-1602 See merge request espressif/esp-idf!37276
2 parents 4f968c3 + dd2bde0 commit 2d1c99e

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11 files changed

+36
-33
lines changed

11 files changed

+36
-33
lines changed

‎components/esp_hw_support/port/esp32/include/soc/rtc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -564,8 +564,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
564564
* used in lightsleep mode.
565565
*
566566
* @param slowclk_period re-calibrated slow clock period
567+
* @param dslp true if initialize for deepsleep request
567568
*/
568-
void rtc_sleep_low_init(uint32_t slowclk_period);
569+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
569570

570571
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
571572
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup

‎components/esp_hw_support/port/esp32/rtc_sleep.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -235,12 +235,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
235235
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
236236
}
237237

238-
void rtc_sleep_low_init(uint32_t slowclk_period)
238+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
239239
{
240240
// set 5 PWC state machine times to fit in main state machine time
241-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
242-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
243-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
241+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
242+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
243+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
244244
}
245245

246246
/* Read back 'reject' status when waking from light or deep sleep */

‎components/esp_hw_support/port/esp32c2/include/soc/rtc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -598,8 +598,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
598598
* used in lightsleep mode.
599599
*
600600
* @param slowclk_period re-calibrated slow clock period
601+
* @param dslp true if initialize for deepsleep request
601602
*/
602-
void rtc_sleep_low_init(uint32_t slowclk_period);
603+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
603604

604605
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup
605606
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup

‎components/esp_hw_support/port/esp32c2/rtc_sleep.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -193,12 +193,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
193193
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
194194
}
195195

196-
void rtc_sleep_low_init(uint32_t slowclk_period)
196+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
197197
{
198198
// set 5 PWC state machine times to fit in main state machine time
199-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
200-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
201-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
199+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
200+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
201+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
202202
}
203203

204204
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

‎components/esp_hw_support/port/esp32c3/include/soc/rtc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -644,8 +644,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
644644
* used in lightsleep mode.
645645
*
646646
* @param slowclk_period re-calibrated slow clock period
647+
* @param dslp true if initialize for deepsleep request
647648
*/
648-
void rtc_sleep_low_init(uint32_t slowclk_period);
649+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
649650

650651
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup
651652
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup

‎components/esp_hw_support/port/esp32c3/rtc_sleep.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -244,12 +244,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
244244
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
245245
}
246246

247-
void rtc_sleep_low_init(uint32_t slowclk_period)
247+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
248248
{
249249
// set 5 PWC state machine times to fit in main state machine time
250-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
251-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
252-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
250+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
251+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
252+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
253253
}
254254

255255
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

‎components/esp_hw_support/port/esp32s2/include/soc/rtc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -669,8 +669,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
669669
* used in lightsleep mode.
670670
*
671671
* @param slowclk_period re-calibrated slow clock period
672+
* @param dslp true if initialize for deepsleep request
672673
*/
673-
void rtc_sleep_low_init(uint32_t slowclk_period);
674+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
674675

675676
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
676677
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup

‎components/esp_hw_support/port/esp32s2/rtc_sleep.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -249,11 +249,11 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
249249
REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
250250
}
251251

252-
void rtc_sleep_low_init(uint32_t slowclk_period)
252+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
253253
{
254-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
255-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
256-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
254+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
255+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
256+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
257257
}
258258

259259
/* Read back 'reject' status when waking from light or deep sleep */

‎components/esp_hw_support/port/esp32s3/include/soc/rtc.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -655,8 +655,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
655655
* used in lightsleep mode.
656656
*
657657
* @param slowclk_period re-calibrated slow clock period
658+
* @param dslp true if initialize for deepsleep request
658659
*/
659-
void rtc_sleep_low_init(uint32_t slowclk_period);
660+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
660661

661662
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
662663
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup

‎components/esp_hw_support/port/esp32s3/rtc_sleep.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -256,12 +256,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
256256
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
257257
}
258258

259-
void rtc_sleep_low_init(uint32_t slowclk_period)
259+
void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
260260
{
261261
// set 5 PWC state machine times to fit in main state machine time
262-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
263-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
264-
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
262+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
263+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
264+
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
265265
}
266266

267267
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

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