test(psram): re-enable 80M psram tests on C5 ECO2

Icarus113 · Icarus113 · commit 2f8cd616cc7a · 2025-05-22T14:52:40.000+08:00
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
@@ -55,6 +55,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
     mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
@@ -52,6 +52,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
     // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
     // in this stage, set divider as 6
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
+    // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid
     mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);
 }
 
diff --git a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults.esp32c5 b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults.esp32c5
@@ -1,3 +1,3 @@
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED_80M=y
 CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
diff --git a/components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32c5 b/components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32c5
@@ -1,3 +1,3 @@
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED_80M=y
 CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
diff --git a/examples/peripherals/lcd/parlio_simulate/sdkconfig.defaults.esp32c5 b/examples/peripherals/lcd/parlio_simulate/sdkconfig.defaults.esp32c5
@@ -1,5 +1,5 @@
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED_80M=y
 # Enabling the following configurations can help increase the PCLK frequency in the case when
 # the Frame Buffer is allocated from the PSRAM and fetched by EDMA
 CONFIG_SPIRAM_XIP_FROM_PSRAM=y

Original file line number	Diff line number	Diff line change
`@@ -55,6 +55,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)`
`55`	`55`	`// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz`
`56`	`56`	`// in this stage, set divider as 6`
`57`	`57`	`_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);`
	`58`	`+ // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid`
`58`	`59`	`mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);`
`59`	`60`	`}`
`60`	`61`
Original file line number	Diff line number	Diff line change
`@@ -52,6 +52,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)`
`52`	`52`	`// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz`
`53`	`53`	`// in this stage, set divider as 6`
`54`	`54`	`_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);`
	`55`	`+ // MSPI0 and MSPI1 share this core clock register, but only setting to MSPI0 register is valid`
`55`	`56`	`mspi_timing_ll_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT);`
`56`	`57`	`}`
`57`	`58`