Merge branch 'bugfix/esp_idf_esp32h4_dualcore_crash' into 'master'

fix(esp_hw_support): resolved setting mie to disable interrupts failed in sleep flow

Closes IDF-14279

See merge request espressif/esp-idf!42605

Author: hbler99

components/esp_hw_support/lowpower/port/esp32c5/rvsleep-frames.h

@@ -83,6 +83,7 @@ STRUCT_BEGIN
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVAL,    mtval)      /* Machine Trap Value */
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MIE,      mie)        /* Machine intr enable */
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MIP,      mip)        /* Machine intr pending */
+    STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH, mintthresh)  /* Machine intr threshold */
 
     STRUCT_FIELD (long, 4, RV_SLP_CTX_PMUFUNC,  pmufunc)    /* A field is used to identify whether it is going
                                                              * to sleep or has just been awakened. We use the
@@ -173,7 +174,6 @@ STRUCT_BEGIN
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MCYCLE,           mcycle)
 
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT,             mtvt)
-    STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH,       mintthresh)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTSTATUS,       mintstatus)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MXSTATUS,         mxstatus)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MHCR,             mhcr)

components/esp_hw_support/lowpower/port/esp32c5/sleep_cpu.c

@@ -60,6 +60,20 @@ FORCE_INLINE_ATTR void restore_mstatus(uint32_t mstatus_val)
     RV_WRITE_CSR(mstatus, mstatus_val);
 }
 
+#if __riscv_zcmp && SOC_CPU_ZCMP_WORKAROUND
+FORCE_INLINE_ATTR uint32_t save_mintthresh_and_disable_global_int(void)
+{
+    /* Due to the reason described in IDF-14279, when mie is set to 0, mintthresh needs to be set to 0xff. */
+    // TODO: IDF-14279 DIG-661
+    return RV_READ_MINTTHRESH_AND_DISABLE_INTR();
+}
+
+FORCE_INLINE_ATTR void restore_mintthresh(uint32_t mintthresh_val)
+{
+    RV_RESTORE_MINTTHRESH(mintthresh_val);
+}
+#endif
+
 static IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(void)
 {
     assert(s_cpu_retention.retent.non_critical_frame);
@@ -128,7 +142,6 @@ static IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(voi
     frame->mcycle     = RV_READ_CSR(mcycle);
 
     frame->mtvt       = RV_READ_CSR(CUSTOM_CSR_MTVT);
-    frame->mintthresh = RV_READ_CSR(CUSTOM_CSR_MINTTHRESH);
     frame->mxstatus   = RV_READ_CSR(CUSTOM_CSR_MXSTATUS);
     frame->mhcr       = RV_READ_CSR(CUSTOM_CSR_MHCR);
     frame->mhint      = RV_READ_CSR(CUSTOM_CSR_MHINT);
@@ -203,7 +216,6 @@ static IRAM_ATTR void rv_core_noncritical_regs_restore(RvCoreNonCriticalSleepFra
     RV_WRITE_CSR(mcycle,   frame->mcycle);
 
     RV_WRITE_CSR(CUSTOM_CSR_MTVT, frame->mtvt);
-    RV_WRITE_CSR(CUSTOM_CSR_MINTTHRESH, frame->mintthresh);
     RV_WRITE_CSR(CUSTOM_CSR_MXSTATUS, frame->mxstatus);
     RV_WRITE_CSR(CUSTOM_CSR_MHCR, frame->mhcr);
     RV_WRITE_CSR(CUSTOM_CSR_MHINT, frame->mhint);
@@ -275,14 +287,14 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
         esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_END, (void *)0);
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
         /* Minus 2 * sizeof(long) is for bypass `pmufunc` and `frame_crc` field */
-        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
 #endif
         REG_WRITE(RTC_SLEEP_WAKE_STUB_ADDR_REG, (uint32_t)rv_core_critical_regs_restore);
         return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
     }
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
     else {
-        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
     }
 #endif
 
@@ -294,6 +306,9 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin
 {
     esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_START, (void *)0);
     uint32_t mstatus = save_mstatus_and_disable_global_int();
+#if __riscv_zcmp && SOC_CPU_ZCMP_WORKAROUND
+    uint32_t mintthresh = save_mintthresh_and_disable_global_int();
+#endif
 
     cpu_domain_dev_regs_save(s_cpu_retention.retent.clic_frame);
     cpu_domain_dev_regs_save(s_cpu_retention.retent.clint_frame);
@@ -314,6 +329,9 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin
     cpu_domain_dev_regs_restore(s_cpu_retention.retent.cache_config_frame);
     cpu_domain_dev_regs_restore(s_cpu_retention.retent.clint_frame);
     cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame);
+#if __riscv_zcmp && SOC_CPU_ZCMP_WORKAROUND
+    restore_mintthresh(mintthresh);
+#endif
     restore_mstatus(mstatus);
     return err;
 }

components/esp_hw_support/lowpower/port/esp32c5/sleep_cpu_asm.S

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 #include "rvsleep-frames.h"
 #include "soc/soc_caps.h"
 #include "sdkconfig.h"
+#include "riscv/csr_clic.h"
 
     .section    .data1,"aw"
     .global     rv_core_critical_regs_frame
@@ -91,6 +92,8 @@ rv_core_critical_regs_save:
     sw      t3, RV_SLP_CTX_MIP(t0)
     csrr    t1, mepc
     sw      t1, RV_SLP_CTX_MEPC(t0)
+    csrr    t2, MINTTHRESH_CSR
+    sw      t2, RV_SLP_CTX_MINTTHRESH(t0)
 
     /*
     !!! Let idf knows it's going to sleep !!!
@@ -162,6 +165,8 @@ rv_core_critical_regs_restore:
     ori     t1, t1, 0x3
     sw      t1, RV_SLP_CTX_PMUFUNC(t0)
 
+    lw      t2, RV_SLP_CTX_MINTTHRESH(t0)
+    csrw    MINTTHRESH_CSR, t2
     lw      t2, RV_SLP_CTX_MEPC(t0)
     csrw    mepc, t2
     lw      t3, RV_SLP_CTX_MIP(t0)

components/esp_hw_support/lowpower/port/esp32c6/sleep_cpu.c

@@ -295,14 +295,14 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
         esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_END, (void *)0);
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
         /* Minus 2 * sizeof(long) is for bypass `pmufunc` and `frame_crc` field */
-        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
 #endif
         REG_WRITE(RTC_SLEEP_WAKE_STUB_ADDR_REG, (uint32_t)rv_core_critical_regs_restore);
         return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
     }
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
     else {
-        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
     }
 #endif
 

components/esp_hw_support/lowpower/port/esp32c61/rvsleep-frames.h

@@ -83,6 +83,7 @@ STRUCT_BEGIN
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVAL,    mtval)      /* Machine Trap Value */
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MIE,      mie)        /* Machine intr enable */
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MIP,      mip)        /* Machine intr pending */
+    STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH, mintthresh)  /* Machine intr threshold */
 
     STRUCT_FIELD (long, 4, RV_SLP_CTX_PMUFUNC,  pmufunc)    /* A field is used to identify whether it is going
                                                              * to sleep or has just been awakened. We use the
@@ -173,7 +174,6 @@ STRUCT_BEGIN
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MCYCLE,           mcycle)
 
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT,             mtvt)
-    STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH,       mintthresh)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTSTATUS,       mintstatus)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MXSTATUS,         mxstatus)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MHCR,             mhcr)

components/esp_hw_support/lowpower/port/esp32c61/sleep_cpu.c

@@ -60,6 +60,20 @@ FORCE_INLINE_ATTR void restore_mstatus(uint32_t mstatus_val)
     RV_WRITE_CSR(mstatus, mstatus_val);
 }
 
+#if __riscv_zcmp && SOC_CPU_ZCMP_WORKAROUND
+FORCE_INLINE_ATTR uint32_t save_mintthresh_and_disable_global_int(void)
+{
+    /* Due to the reason described in IDF-14279, when mie is set to 0, mintthresh needs to be set to 0xff. */
+    // TODO: IDF-14279 DIG-661
+    return RV_READ_MINTTHRESH_AND_DISABLE_INTR();
+}
+
+FORCE_INLINE_ATTR void restore_mintthresh(uint32_t mintthresh_val)
+{
+    RV_RESTORE_MINTTHRESH(mintthresh_val);
+}
+#endif
+
 static IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(void)
 {
     assert(s_cpu_retention.retent.non_critical_frame);
@@ -128,7 +142,6 @@ static IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(voi
     frame->mcycle     = RV_READ_CSR(mcycle);
 
     frame->mtvt       = RV_READ_CSR(CUSTOM_CSR_MTVT);
-    frame->mintthresh = RV_READ_CSR(CUSTOM_CSR_MINTTHRESH);
     frame->mxstatus   = RV_READ_CSR(CUSTOM_CSR_MXSTATUS);
     frame->mhcr       = RV_READ_CSR(CUSTOM_CSR_MHCR);
     frame->mhint      = RV_READ_CSR(CUSTOM_CSR_MHINT);
@@ -203,7 +216,6 @@ static IRAM_ATTR void rv_core_noncritical_regs_restore(RvCoreNonCriticalSleepFra
     RV_WRITE_CSR(mcycle,   frame->mcycle);
 
     RV_WRITE_CSR(CUSTOM_CSR_MTVT, frame->mtvt);
-    RV_WRITE_CSR(CUSTOM_CSR_MINTTHRESH, frame->mintthresh);
     RV_WRITE_CSR(CUSTOM_CSR_MXSTATUS, frame->mxstatus);
     RV_WRITE_CSR(CUSTOM_CSR_MHCR, frame->mhcr);
     RV_WRITE_CSR(CUSTOM_CSR_MHINT, frame->mhint);
@@ -275,14 +287,14 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
         esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_END, (void *)0);
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
         /* Minus 2 * sizeof(long) is for bypass `pmufunc` and `frame_crc` field */
-        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
 #endif
         REG_WRITE(RTC_SLEEP_WAKE_STUB_ADDR_REG, (uint32_t)rv_core_critical_regs_restore);
         return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
     }
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
     else {
-        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
     }
 #endif
 
@@ -294,6 +306,9 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin
 {
     esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_START, (void *)0);
     uint32_t mstatus = save_mstatus_and_disable_global_int();
+#if __riscv_zcmp && SOC_CPU_ZCMP_WORKAROUND
+    uint32_t mintthresh = save_mintthresh_and_disable_global_int();
+#endif
 
     cpu_domain_dev_regs_save(s_cpu_retention.retent.clic_frame);
     cpu_domain_dev_regs_save(s_cpu_retention.retent.clint_frame);
@@ -314,6 +329,9 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin
     cpu_domain_dev_regs_restore(s_cpu_retention.retent.cache_config_frame);
     cpu_domain_dev_regs_restore(s_cpu_retention.retent.clint_frame);
     cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame);
+#if __riscv_zcmp && SOC_CPU_ZCMP_WORKAROUND
+    restore_mintthresh(mintthresh);
+#endif
     restore_mstatus(mstatus);
     return err;
 }

components/esp_hw_support/lowpower/port/esp32c61/sleep_cpu_asm.S

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 #include "rvsleep-frames.h"
 #include "soc/soc_caps.h"
 #include "sdkconfig.h"
+#include "riscv/csr_clic.h"
 
     .section    .data1,"aw"
     .global     rv_core_critical_regs_frame
@@ -91,6 +92,8 @@ rv_core_critical_regs_save:
     sw      t3, RV_SLP_CTX_MIP(t0)
     csrr    t1, mepc
     sw      t1, RV_SLP_CTX_MEPC(t0)
+    csrr    t2, MINTTHRESH_CSR
+    sw      t2, RV_SLP_CTX_MINTTHRESH(t0)
 
     /*
     !!! Let idf knows it's going to sleep !!!
@@ -162,6 +165,8 @@ rv_core_critical_regs_restore:
     ori     t1, t1, 0x3
     sw      t1, RV_SLP_CTX_PMUFUNC(t0)
 
+    lw      t2, RV_SLP_CTX_MINTTHRESH(t0)
+    csrw    MINTTHRESH_CSR, t2
     lw      t2, RV_SLP_CTX_MEPC(t0)
     csrw    mepc, t2
     lw      t3, RV_SLP_CTX_MIP(t0)

components/esp_hw_support/lowpower/port/esp32h2/sleep_cpu.c

@@ -295,14 +295,14 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
         esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_END, (void *)0);
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
         /* Minus 2 * sizeof(long) is for bypass `pmufunc` and `frame_crc` field */
-        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
 #endif
         REG_WRITE(RTC_SLEEP_WAKE_STUB_ADDR_REG, (uint32_t)rv_core_critical_regs_restore);
         return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
     }
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
     else {
-        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
     }
 #endif
 

components/esp_hw_support/lowpower/port/esp32h21/sleep_cpu.c

@@ -294,14 +294,14 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
         esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_END, (void *)0);
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
         /* Minus 2 * sizeof(long) is for bypass `pmufunc` and `frame_crc` field */
-        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        update_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
 #endif
         REG_WRITE(RTC_SLEEP_WAKE_STUB_ADDR_REG, (uint32_t)rv_core_critical_regs_restore);
         return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
     }
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
     else {
-        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_FRMSZ - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
+        validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
     }
 #endif
 

components/esp_hw_support/lowpower/port/esp32h4/rvsleep-frames.h

@@ -83,6 +83,7 @@ STRUCT_BEGIN
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVAL,    mtval)      /* Machine Trap Value */
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MIE,      mie)        /* Machine intr enable */
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MIP,      mip)        /* Machine intr pending */
+    STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH, mintthresh)  /* Machine intr threshold */
 
     STRUCT_FIELD (long, 4, RV_SLP_CTX_PMUFUNC,  pmufunc)    /* A field is used to identify whether it is going
                                                              * to sleep or has just been awakened. We use the
@@ -197,7 +198,6 @@ STRUCT_BEGIN
 
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MCYCLE,           mcycle)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT,             mtvt)
-    STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH,       mintthresh)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MXSTATUS,         mxstatus)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MHCR,             mhcr)
     STRUCT_FIELD (long, 4, RV_SLP_CTX_MHINT,            mhint)