Merge branch 'feat/h4_introduce_step2_3' into 'master'

feat(esp32h4): add soc register header files (stage 3/8, part 3/3)

See merge request espressif/esp-idf!37092

Author: Kainarx

components/riscv/include/riscv/rv_utils.h

@@ -9,7 +9,9 @@
 #include <stdint.h>
 
 #include "soc/soc_caps.h"
+#if SOC_ASSIST_DEBUG_SUPPORTED
 #include "soc/assist_debug_reg.h"
+#endif
 #include "soc/interrupt_reg.h"
 #include "esp_attr.h"
 #include "riscv/csr.h"
@@ -405,7 +407,11 @@ FORCE_INLINE_ATTR bool rv_utils_is_trigger_fired(int id)
 
 FORCE_INLINE_ATTR bool rv_utils_dbgr_is_attached(void)
 {
+#if SOC_ASSIST_DEBUG_SUPPORTED
     return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
+#else
+    return false;
+#endif
 }
 
 FORCE_INLINE_ATTR void rv_utils_dbgr_break(void)