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mythbuster5mythbuster5
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Merge branch 'refactor/update_locks' into 'master'
refactor(hw_support): Use esp_os_enter_critical instead of portENTER_CRITICAL_SAFE Closes IDF-13397 See merge request espressif/esp-idf!39922
2 parents dcd29e5 + 3041f33 commit 35f2cca

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44 files changed

+549
-492
lines changed

‎components/esp_hw_support/adc_share_hw_ctrl.c‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -29,6 +29,7 @@
2929
#include "esp_private/adc_share_hw_ctrl.h"
3030
#include "esp_private/sar_periph_ctrl.h"
3131
#include "esp_private/periph_ctrl.h"
32+
#include "esp_private/critical_section.h"
3233
#include "soc/periph_defs.h"
3334
//For calibration
3435
#if CONFIG_IDF_TARGET_ESP32S2
@@ -79,11 +80,11 @@ void adc_calc_hw_calibration_code(adc_unit_t adc_n, adc_atten_t atten)
7980
else {
8081
ESP_EARLY_LOGD(TAG, "Calibration eFuse is not configured, use self-calibration for ICode");
8182
sar_periph_ctrl_adc_oneshot_power_acquire();
82-
portENTER_CRITICAL(&rtc_spinlock);
83+
esp_os_enter_critical(&rtc_spinlock);
8384
adc_ll_pwdet_set_cct(ADC_LL_PWDET_CCT_DEFAULT);
8485
const bool internal_gnd = true;
8586
init_code = adc_hal_self_calibration(adc_n, atten, internal_gnd);
86-
portEXIT_CRITICAL(&rtc_spinlock);
87+
esp_os_exit_critical(&rtc_spinlock);
8788
sar_periph_ctrl_adc_oneshot_power_release();
8889
}
8990
#else
@@ -193,7 +194,7 @@ esp_err_t adc2_wifi_release(void)
193194
return ESP_OK;
194195
}
195196

196-
static portMUX_TYPE s_spinlock = portMUX_INITIALIZER_UNLOCKED;
197+
static portMUX_TYPE __attribute__((unused)) s_spinlock = portMUX_INITIALIZER_UNLOCKED;
197198

198199
/*------------------------------------------------------------------------------
199200
* For those who use APB_SARADC periph
@@ -202,7 +203,7 @@ static int s_adc_digi_ctrlr_cnt;
202203

203204
void adc_apb_periph_claim(void)
204205
{
205-
portENTER_CRITICAL(&s_spinlock);
206+
esp_os_enter_critical(&s_spinlock);
206207
s_adc_digi_ctrlr_cnt++;
207208
if (s_adc_digi_ctrlr_cnt == 1) {
208209
ADC_BUS_CLK_ATOMIC() {
@@ -214,12 +215,12 @@ void adc_apb_periph_claim(void)
214215
}
215216
}
216217

217-
portEXIT_CRITICAL(&s_spinlock);
218+
esp_os_exit_critical(&s_spinlock);
218219
}
219220

220221
void adc_apb_periph_free(void)
221222
{
222-
portENTER_CRITICAL(&s_spinlock);
223+
esp_os_enter_critical(&s_spinlock);
223224
s_adc_digi_ctrlr_cnt--;
224225
if (s_adc_digi_ctrlr_cnt == 0) {
225226
ADC_BUS_CLK_ATOMIC() {
@@ -229,10 +230,10 @@ void adc_apb_periph_free(void)
229230
#endif
230231
}
231232
} else if (s_adc_digi_ctrlr_cnt < 0) {
232-
portEXIT_CRITICAL(&s_spinlock);
233+
esp_os_exit_critical(&s_spinlock);
233234
ESP_LOGE(TAG, "%s called, but `s_adc_digi_ctrlr_cnt == 0`", __func__);
234235
abort();
235236
}
236237

237-
portEXIT_CRITICAL(&s_spinlock);
238+
esp_os_exit_critical(&s_spinlock);
238239
}

‎components/esp_hw_support/clk_ctrl_os.c‎

Lines changed: 19 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include "soc/rtc.h"
1010
#include "esp_ldo_regulator.h"
1111
#include "esp_private/esp_clk_tree_common.h"
12+
#include "esp_private/critical_section.h"
1213
#include "esp_check.h"
1314
#include "hal/clk_tree_hal.h"
1415
#include "hal/clk_tree_ll.h"
@@ -20,7 +21,7 @@
2021
static const char *TAG = "clk_ctrl_os";
2122
#endif
2223

23-
static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
24+
static portMUX_TYPE __attribute__((unused)) periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
2425

2526
static uint8_t s_periph_ref_counts = 0;
2627
static uint32_t s_rc_fast_freq_hz = 0; // Frequency of the RC_FAST clock in Hz
@@ -37,20 +38,20 @@ static esp_ldo_channel_handle_t s_ldo_chan = NULL;
3738

3839
bool periph_rtc_dig_clk8m_enable(void)
3940
{
40-
portENTER_CRITICAL(&periph_spinlock);
41+
esp_os_enter_critical(&periph_spinlock);
4142
if (s_periph_ref_counts == 0) {
4243
rtc_dig_clk8m_enable();
4344
#if SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
4445
s_rc_fast_freq_hz = esp_clk_tree_rc_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT);
4546
if (s_rc_fast_freq_hz == 0) {
4647
rtc_dig_clk8m_disable();
47-
portEXIT_CRITICAL(&periph_spinlock);
48+
esp_os_exit_critical(&periph_spinlock);
4849
return false;
4950
}
5051
#endif //SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
5152
}
5253
s_periph_ref_counts++;
53-
portEXIT_CRITICAL(&periph_spinlock);
54+
esp_os_exit_critical(&periph_spinlock);
5455
return true;
5556
}
5657

@@ -66,39 +67,39 @@ uint32_t periph_rtc_dig_clk8m_get_freq(void)
6667

6768
void periph_rtc_dig_clk8m_disable(void)
6869
{
69-
portENTER_CRITICAL(&periph_spinlock);
70+
esp_os_enter_critical(&periph_spinlock);
7071
assert(s_periph_ref_counts > 0);
7172
s_periph_ref_counts--;
7273
if (s_periph_ref_counts == 0) {
7374
s_rc_fast_freq_hz = 0;
7475
rtc_dig_clk8m_disable();
7576
}
76-
portEXIT_CRITICAL(&periph_spinlock);
77+
esp_os_exit_critical(&periph_spinlock);
7778
}
7879

7980
#if SOC_CLK_APLL_SUPPORTED
8081
void periph_rtc_apll_acquire(void)
8182
{
82-
portENTER_CRITICAL(&periph_spinlock);
83+
esp_os_enter_critical(&periph_spinlock);
8384
s_apll_ref_cnt++;
8485
if (s_apll_ref_cnt == 1) {
8586
// For the first time enable APLL, need to set power up
8687
rtc_clk_apll_enable(true);
8788
}
88-
portEXIT_CRITICAL(&periph_spinlock);
89+
esp_os_exit_critical(&periph_spinlock);
8990
}
9091

9192
void periph_rtc_apll_release(void)
9293
{
93-
portENTER_CRITICAL(&periph_spinlock);
94+
esp_os_enter_critical(&periph_spinlock);
9495
assert(s_apll_ref_cnt > 0);
9596
s_apll_ref_cnt--;
9697
if (s_apll_ref_cnt == 0) {
9798
// If there is no peripheral using APLL, shut down the power
9899
s_cur_apll_freq_hz = 0;
99100
rtc_clk_apll_enable(false);
100101
}
101-
portEXIT_CRITICAL(&periph_spinlock);
102+
esp_os_exit_critical(&periph_spinlock);
102103
}
103104

104105
esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz)
@@ -113,7 +114,7 @@ esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz
113114

114115
ESP_RETURN_ON_FALSE(apll_freq, ESP_ERR_INVALID_ARG, TAG, "APLL coefficients calculate failed");
115116
bool need_config = true;
116-
portENTER_CRITICAL(&periph_spinlock);
117+
esp_os_enter_critical(&periph_spinlock);
117118
/* If APLL is not in use or only one peripheral in use, its frequency can be changed as will
118119
* But when more than one peripheral refers APLL, its frequency is not allowed to change once it is set */
119120
if (s_cur_apll_freq_hz == 0 || s_apll_ref_cnt < 2) {
@@ -122,7 +123,7 @@ esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz
122123
apll_freq = s_cur_apll_freq_hz;
123124
need_config = false;
124125
}
125-
portEXIT_CRITICAL(&periph_spinlock);
126+
esp_os_exit_critical(&periph_spinlock);
126127
*real_freq_hz = apll_freq;
127128

128129
if (need_config) {
@@ -150,13 +151,13 @@ esp_err_t IRAM_ATTR periph_rtc_mpll_acquire(void)
150151
ESP_RETURN_ON_ERROR(esp_ldo_acquire_channel(&ldo_mpll_config, &s_ldo_chan), TAG, "acquire internal LDO for MPLL failed");
151152
#endif
152153

153-
portENTER_CRITICAL(&periph_spinlock);
154+
esp_os_enter_critical(&periph_spinlock);
154155
s_mpll_ref_cnt++;
155156
if (s_mpll_ref_cnt == 1) {
156157
// For the first time enable MPLL, need to set power up
157158
rtc_clk_mpll_enable();
158159
}
159-
portEXIT_CRITICAL(&periph_spinlock);
160+
esp_os_exit_critical(&periph_spinlock);
160161
return ESP_OK;
161162
}
162163

@@ -167,15 +168,15 @@ void periph_rtc_mpll_release(void)
167168
esp_ldo_release_channel(s_ldo_chan);
168169
}
169170
#endif
170-
portENTER_CRITICAL(&periph_spinlock);
171+
esp_os_enter_critical(&periph_spinlock);
171172
assert(s_mpll_ref_cnt > 0);
172173
s_mpll_ref_cnt--;
173174
if (s_mpll_ref_cnt == 0) {
174175
// If there is no peripheral using MPLL, shut down the power
175176
s_cur_mpll_freq_hz = 0;
176177
rtc_clk_mpll_disable();
177178
}
178-
portEXIT_CRITICAL(&periph_spinlock);
179+
esp_os_exit_critical(&periph_spinlock);
179180
}
180181

181182
esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq_hz, uint32_t *real_freq_hz)
@@ -185,7 +186,7 @@ esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq_hz, uint32_t *re
185186
// Guarantee 'periph_rtc_apll_acquire' has been called before set apll freq
186187
assert(s_mpll_ref_cnt > 0);
187188

188-
portENTER_CRITICAL(&periph_spinlock);
189+
esp_os_enter_critical(&periph_spinlock);
189190
if (s_cur_mpll_freq_hz == expt_freq_hz) {
190191
goto end;
191192
}
@@ -202,7 +203,7 @@ esp_err_t IRAM_ATTR periph_rtc_mpll_freq_set(uint32_t expt_freq_hz, uint32_t *re
202203
if (real_freq_hz != NULL) {
203204
*real_freq_hz = s_cur_mpll_freq_hz;
204205
}
205-
portEXIT_CRITICAL(&periph_spinlock);
206+
esp_os_exit_critical(&periph_spinlock);
206207
return ret;
207208
}
208209
#endif // SOC_CLK_MPLL_SUPPORTED

‎components/esp_hw_support/dma/async_memcpy_cp_dma.c‎

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -21,6 +21,7 @@
2121
#include "esp_async_memcpy_priv.h"
2222
#include "esp_private/gdma_link.h"
2323
#include "esp_private/esp_dma_utils.h"
24+
#include "esp_private/critical_section.h"
2425
#include "hal/cp_dma_hal.h"
2526
#include "hal/cp_dma_ll.h"
2627

@@ -147,12 +148,12 @@ static esp_err_t mcp_cpdma_del(async_memcpy_context_t *ctx)
147148
static async_memcpy_transaction_t *try_pop_trans_from_ready_queue(async_memcpy_cpdma_context_t *mcp_dma)
148149
{
149150
async_memcpy_transaction_t *trans = NULL;
150-
portENTER_CRITICAL_SAFE(&mcp_dma->spin_lock);
151+
esp_os_enter_critical_safe(&mcp_dma->spin_lock);
151152
trans = STAILQ_FIRST(&mcp_dma->ready_queue_head);
152153
if (trans) {
153154
STAILQ_REMOVE_HEAD(&mcp_dma->ready_queue_head, ready_queue_entry);
154155
}
155-
portEXIT_CRITICAL_SAFE(&mcp_dma->spin_lock);
156+
esp_os_exit_critical_safe(&mcp_dma->spin_lock);
156157
return trans;
157158
}
158159

@@ -182,12 +183,12 @@ static void try_start_pending_transaction(async_memcpy_cpdma_context_t *mcp_dma)
182183
static async_memcpy_transaction_t *try_pop_trans_from_idle_queue(async_memcpy_cpdma_context_t *mcp_dma)
183184
{
184185
async_memcpy_transaction_t *trans = NULL;
185-
portENTER_CRITICAL_SAFE(&mcp_dma->spin_lock);
186+
esp_os_enter_critical_safe(&mcp_dma->spin_lock);
186187
trans = STAILQ_FIRST(&mcp_dma->idle_queue_head);
187188
if (trans) {
188189
STAILQ_REMOVE_HEAD(&mcp_dma->idle_queue_head, idle_queue_entry);
189190
}
190-
portEXIT_CRITICAL_SAFE(&mcp_dma->spin_lock);
191+
esp_os_exit_critical_safe(&mcp_dma->spin_lock);
191192
return trans;
192193
}
193194

@@ -266,10 +267,10 @@ static esp_err_t mcp_cpdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *
266267
trans->cb = cb_isr;
267268
trans->cb_args = cb_args;
268269

269-
portENTER_CRITICAL(&mcp_dma->spin_lock);
270+
esp_os_enter_critical(&mcp_dma->spin_lock);
270271
// insert the trans to ready queue
271272
STAILQ_INSERT_TAIL(&mcp_dma->ready_queue_head, trans, ready_queue_entry);
272-
portEXIT_CRITICAL(&mcp_dma->spin_lock);
273+
esp_os_exit_critical(&mcp_dma->spin_lock);
273274

274275
// check driver state, if there's no running transaction, start a new one
275276
try_start_pending_transaction(mcp_dma);
@@ -279,9 +280,9 @@ static esp_err_t mcp_cpdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *
279280
err:
280281
if (trans) {
281282
// return back the trans to idle queue
282-
portENTER_CRITICAL(&mcp_dma->spin_lock);
283+
esp_os_enter_critical(&mcp_dma->spin_lock);
283284
STAILQ_INSERT_TAIL(&mcp_dma->idle_queue_head, trans, idle_queue_entry);
284-
portEXIT_CRITICAL(&mcp_dma->spin_lock);
285+
esp_os_exit_critical(&mcp_dma->spin_lock);
285286
}
286287
return ret;
287288
}
@@ -311,10 +312,10 @@ static void mcp_default_isr_handler(void *args)
311312
}
312313
trans->cb = NULL;
313314

314-
portENTER_CRITICAL_ISR(&mcp_dma->spin_lock);
315+
esp_os_enter_critical_isr(&mcp_dma->spin_lock);
315316
// insert the trans object to the idle queue
316317
STAILQ_INSERT_TAIL(&mcp_dma->idle_queue_head, trans, idle_queue_entry);
317-
portEXIT_CRITICAL_ISR(&mcp_dma->spin_lock);
318+
esp_os_exit_critical_isr(&mcp_dma->spin_lock);
318319

319320
atomic_store(&mcp_dma->fsm, MCP_FSM_IDLE);
320321
}

‎components/esp_hw_support/dma/async_memcpy_gdma.c‎

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include "esp_private/gdma.h"
1919
#include "esp_private/gdma_link.h"
2020
#include "esp_private/esp_dma_utils.h"
21+
#include "esp_private/critical_section.h"
2122
#include "esp_memory_utils.h"
2223
#include "esp_cache.h"
2324
#include "esp_async_memcpy.h"
@@ -237,12 +238,12 @@ static esp_err_t mcp_gdma_del(async_memcpy_context_t *ctx)
237238
static async_memcpy_transaction_t *try_pop_trans_from_ready_queue(async_memcpy_gdma_context_t *mcp_gdma)
238239
{
239240
async_memcpy_transaction_t *trans = NULL;
240-
portENTER_CRITICAL_SAFE(&mcp_gdma->spin_lock);
241+
esp_os_enter_critical_safe(&mcp_gdma->spin_lock);
241242
trans = STAILQ_FIRST(&mcp_gdma->ready_queue_head);
242243
if (trans) {
243244
STAILQ_REMOVE_HEAD(&mcp_gdma->ready_queue_head, ready_queue_entry);
244245
}
245-
portEXIT_CRITICAL_SAFE(&mcp_gdma->spin_lock);
246+
esp_os_exit_critical_safe(&mcp_gdma->spin_lock);
246247
return trans;
247248
}
248249

@@ -270,12 +271,12 @@ static void try_start_pending_transaction(async_memcpy_gdma_context_t *mcp_gdma)
270271
static async_memcpy_transaction_t *try_pop_trans_from_idle_queue(async_memcpy_gdma_context_t *mcp_gdma)
271272
{
272273
async_memcpy_transaction_t *trans = NULL;
273-
portENTER_CRITICAL_SAFE(&mcp_gdma->spin_lock);
274+
esp_os_enter_critical_safe(&mcp_gdma->spin_lock);
274275
trans = STAILQ_FIRST(&mcp_gdma->idle_queue_head);
275276
if (trans) {
276277
STAILQ_REMOVE_HEAD(&mcp_gdma->idle_queue_head, idle_queue_entry);
277278
}
278-
portEXIT_CRITICAL_SAFE(&mcp_gdma->spin_lock);
279+
esp_os_exit_critical_safe(&mcp_gdma->spin_lock);
279280
return trans;
280281
}
281282

@@ -413,10 +414,10 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s
413414
trans->cb = cb_isr;
414415
trans->cb_args = cb_args;
415416

416-
portENTER_CRITICAL(&mcp_gdma->spin_lock);
417+
esp_os_enter_critical(&mcp_gdma->spin_lock);
417418
// insert the trans to ready queue
418419
STAILQ_INSERT_TAIL(&mcp_gdma->ready_queue_head, trans, ready_queue_entry);
419-
portEXIT_CRITICAL(&mcp_gdma->spin_lock);
420+
esp_os_exit_critical(&mcp_gdma->spin_lock);
420421

421422
// check driver state, if there's no running transaction, start a new one
422423
try_start_pending_transaction(mcp_gdma);
@@ -426,9 +427,9 @@ static esp_err_t mcp_gdma_memcpy(async_memcpy_context_t *ctx, void *dst, void *s
426427
err:
427428
if (trans) {
428429
// return back the trans to idle queue
429-
portENTER_CRITICAL(&mcp_gdma->spin_lock);
430+
esp_os_enter_critical(&mcp_gdma->spin_lock);
430431
STAILQ_INSERT_TAIL(&mcp_gdma->idle_queue_head, trans, idle_queue_entry);
431-
portEXIT_CRITICAL(&mcp_gdma->spin_lock);
432+
esp_os_exit_critical(&mcp_gdma->spin_lock);
432433
}
433434
return ret;
434435
}
@@ -456,10 +457,10 @@ static bool mcp_gdma_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_
456457
}
457458
trans->cb = NULL;
458459

459-
portENTER_CRITICAL_ISR(&mcp_gdma->spin_lock);
460+
esp_os_enter_critical_isr(&mcp_gdma->spin_lock);
460461
// insert the trans object to the idle queue
461462
STAILQ_INSERT_TAIL(&mcp_gdma->idle_queue_head, trans, idle_queue_entry);
462-
portEXIT_CRITICAL_ISR(&mcp_gdma->spin_lock);
463+
esp_os_exit_critical_isr(&mcp_gdma->spin_lock);
463464

464465
atomic_store(&mcp_gdma->fsm, MCP_FSM_IDLE);
465466
}

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