Skip to content

Commit 3606d9e

Browse files
wancklwanckl
committed
Merge branch 'fix/soc_and_iomux_macro_refactor' into 'master'
fix(driver_spi): move spi related macros out from soc.h and iomux_reg.h See merge request espressif/esp-idf!32953
2 parents 6bfa408 + 19c6e77 commit 3606d9e

File tree

54 files changed

+369
-385
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

54 files changed

+369
-385
lines changed

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -28,12 +28,12 @@
2828
#include "bootloader_flash_priv.h"
2929
#include "bootloader_init.h"
3030

31-
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
32-
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
33-
#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
34-
#define FLASH_SPID_IO SPI_D_GPIO_NUM
35-
#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
36-
#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
31+
#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
32+
#define FLASH_CS_IO MSPI_IOMUX_PIN_NUM_CS0
33+
#define FLASH_SPIQ_IO MSPI_IOMUX_PIN_NUM_MISO
34+
#define FLASH_SPID_IO MSPI_IOMUX_PIN_NUM_MOSI
35+
#define FLASH_SPIWP_IO MSPI_IOMUX_PIN_NUM_WP
36+
#define FLASH_SPIHD_IO MSPI_IOMUX_PIN_NUM_HD
3737

3838
void bootloader_flash_update_id(void)
3939
{
@@ -98,15 +98,15 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
9898
} else {
9999
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
100100
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
101-
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
102-
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
103-
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
104-
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
105-
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
106-
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
107-
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
108-
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
109-
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
101+
esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
102+
esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
103+
esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
104+
esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
105+
esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
106+
esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
107+
esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
108+
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
109+
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
110110
//select pin function gpio
111111
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
112112
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
@@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void)
190190
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
191191
return ESP32_PICO_V3_GPIO;
192192
default:
193-
return SPI_WP_GPIO_NUM;
193+
return MSPI_IOMUX_PIN_NUM_WP;
194194
}
195195
#endif
196196
}

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -88,12 +88,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
8888
{
8989
// IDF-4066
9090
const uint32_t spiconfig = 0;
91-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
92-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
93-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
94-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
95-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
96-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
91+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
92+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
93+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
94+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
95+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
96+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
9797
if (spiconfig == 0) {
9898

9999
}

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -92,12 +92,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
9292
{
9393
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
9494
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
95-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
96-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
97-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
98-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
99-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
100-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
95+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
96+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
97+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
98+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
99+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
100+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
101101
if (spiconfig == 0) {
102102

103103
} else {

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -74,12 +74,12 @@ static const char *TAG = "boot.esp32c5";
7474

7575
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
7676
{
77-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
78-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
79-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
80-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
81-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
82-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
77+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
78+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
79+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
80+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
81+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
82+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
8383
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
8484
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
8585
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -69,12 +69,12 @@ static const char *TAG = "boot.esp32c6";
6969

7070
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
7171
{
72-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
73-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
74-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
75-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
76-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
77-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
72+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
73+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
74+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
75+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
76+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
77+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
7878
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
7979
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
8080
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -70,12 +70,12 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
7070

7171
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
7272
{
73-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
74-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
75-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
76-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
77-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
78-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
73+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
74+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
75+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
76+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
77+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
78+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
7979
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
8080
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
8181
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -70,12 +70,12 @@ static const char *TAG = "boot.esp32h2";
7070

7171
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
7272
{
73-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
74-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
75-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
76-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
77-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
78-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
73+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
74+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
75+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
76+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
77+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
78+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
7979
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
8080
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
8181
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -66,12 +66,12 @@ static const char *TAG = "boot.esp32p4";
6666

6767
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
6868
{
69-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
70-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
71-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
72-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
73-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
74-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
69+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
70+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
71+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
72+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
73+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
74+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
7575
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
7676
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
7777
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -94,12 +94,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
9494
{
9595
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
9696
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
97-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
98-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
99-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
100-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
101-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
102-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
97+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
98+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
99+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
100+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
101+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
102+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
103103
if (spiconfig == 0) {
104104

105105
} else {

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -105,12 +105,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
105105
{
106106
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
107107
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
108-
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
109-
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
110-
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
111-
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
112-
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
113-
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
108+
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
109+
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
110+
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
111+
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
112+
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
113+
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
114114
if (spiconfig == 0) {
115115

116116
} else {

0 commit comments

Comments
 (0)