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Merge branch 'feat/h4_introduce_step2_2' into 'master'
feat(esp32h4): add soc register header files (stage 3/8, part 2/3) See merge request espressif/esp-idf!37030
2 parents 7e93f4b + d68fcf1 commit 36335e3

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components/soc/esp32h4/include/soc/gpio_sig_map.h

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//Interrupt hardware source table
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//This table is decided by hardware, don't touch this.
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typedef enum {
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ETS_WIFI_MAC_INTR_SOURCE,
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ETS_WIFI_MAC_NMI_SOURCE,
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ETS_WIFI_PWR_INTR_SOURCE,
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ETS_WIFI_BB_INTR_SOURCE,
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ETS_BT_MAC_INTR_SOURCE,
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ETS_BT_BB_INTR_SOURCE,
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ETS_BT_BB_NMI_SOURCE,
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ETS_LP_TIMER_INTR_SOURCE,
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ETS_COEX_INTR_SOURCE,
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ETS_BLE_TIMER_INTR_SOURCE,
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ETS_BLE_SEC_INTR_SOURCE,
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ETS_I2C_MST_INTR_SOURCE,
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ETS_ZB_MAC_INTR_SOURCE,
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ETS_MODEM_APB_TIMEOUT_INTR_SOURCE,
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ETS_BT_MAC_INT1_SOURCE,
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ETS_PMU_INTR_SOURCE,
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ETS_EFUSE_INTR_SOURCE,
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ETS_LP_RTC_TIMER_INTR_SOURCE,
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ETS_LP_RTC_BLE_TIMER_INTR_SOURCE,
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ETS_LP_WDT_INTR_SOURCE,
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ETS_TOUCH_INTR_SOURCE,
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ETS_HUK_INTR_SOURCE,
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ETS_CPU_INTR_FROM_CPU_0_SOURCE,
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ETS_CPU_INTR_FROM_CPU_1_SOURCE,
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ETS_CPU_INTR_FROM_CPU_2_SOURCE,
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ETS_CPU_INTR_FROM_CPU_3_SOURCE,
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ETS_BUS_MONITOR_INTR_SOURCE,
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ETS_CORE0_TRACE_INTR_SOURCE,
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ETS_CORE1_TRACE_INTR_SOURCE,
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ETS_CACHE_INTR_SOURCE,
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ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
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ETS_GPIO_INTERRUPT_PRO_SOURCE,
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ETS_GPIO_INTERRUPT_2_SOURCE,
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ETS_PAU_INTR_SOURCE,
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ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
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ETS_HP_APM_M0_INTR_SOURCE,
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ETS_HP_APM_M1_INTR_SOURCE,
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ETS_HP_APM_M2_INTR_SOURCE,
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ETS_HP_APM_M3_INTR_SOURCE,
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ETS_HP_APM_M4_INTR_SOURCE,
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ETS_CPU_APM_M0_INTR_SOURCE,
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ETS_CPU_APM_M1_INTR_SOURCE,
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ETS_CPU_APM_M2_INTR_SOURCE,
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ETS_CPU_APM_M3_INTR_SOURCE,
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ETS_MSPI_INTR_SOURCE,
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ETS_I2S_INTR_SOURCE,
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ETS_UHCI0_INTR_SOURCE,
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ETS_UART0_INTR_SOURCE,
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ETS_UART1_INTR_SOURCE,
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ETS_LEDC_INTR_SOURCE,
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ETS_TWAI0_INTR_SOURCE,
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ETS_TWAI0_TIMER_INTR_SOURCE,
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ETS_USB_SERIAL_JTAG_INTR_SOURCE,
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ETS_RMT_INTR_SOURCE,
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ETS_I2C_EXT0_INTR_SOURCE,
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ETS_I2C_EXT1_INTR_SOURCE,
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ETS_TG0_T0_INTR_SOURCE,
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ETS_TG0_WDT_INTR_SOURCE,
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ETS_TG1_T0_INTR_SOURCE,
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ETS_TG1_WDT_INTR_SOURCE,
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ETS_SYSTIMER_TARGET0_INTR_SOURCE,
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ETS_SYSTIMER_TARGET1_INTR_SOURCE,
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ETS_SYSTIMER_TARGET2_INTR_SOURCE,
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ETS_APB_ADC_INTR_SOURCE,
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ETS_PWM0_INTR_SOURCE,
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ETS_PWM1_INTR_SOURCE,
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ETS_PCNT_INTR_SOURCE,
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ETS_PARL_IO_TX_INTR_SOURCE,
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ETS_PARL_IO_RX_INTR_SOURCE,
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ETS_USB_OTG11_INTR_SOURCE,
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ETS_ASRC_CHNL0_INTR_SOURCE,
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ETS_ASRC_CHNL1_INTR_SOURCE,
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ETS_ZERO_DET_INTR_SOURCE,
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ETS_DMA_IN_CH0_INTR_SOURCE,
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ETS_DMA_IN_CH1_INTR_SOURCE,
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ETS_DMA_IN_CH2_INTR_SOURCE,
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ETS_DMA_IN_CH3_INTR_SOURCE,
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ETS_DMA_IN_CH4_INTR_SOURCE,
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ETS_DMA_OUT_CH0_INTR_SOURCE,
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ETS_DMA_OUT_CH1_INTR_SOURCE,
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ETS_DMA_OUT_CH2_INTR_SOURCE,
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ETS_DMA_OUT_CH3_INTR_SOURCE,
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ETS_DMA_OUT_CH4_INTR_SOURCE,
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ETS_GPSPI2_INTR_SOURCE,
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ETS_GPSPI3_INTR_SOURCE,
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ETS_AES_INTR_SOURCE,
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ETS_SHA_INTR_SOURCE,
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ETS_ECC_INTR_SOURCE,
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ETS_ECDSA_INTR_SOURCE,
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ETS_KM_INTR_SOURCE,
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ETS_MAX_INTR_SOURCE,
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} periph_interrput_t;
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extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
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#ifdef __cplusplus
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}
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#endif
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#define PMU_ICG_APB_ENA_SEC 0
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#define PMU_ICG_APB_ENA_GDMA 1
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#define PMU_ICG_APB_ENA_SPI2 2
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#define PMU_ICG_APB_ENA_INTMTX 3
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#define PMU_ICG_APB_ENA_I2S 4
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#define PMU_ICG_APB_ENA_MSPI 5
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#define PMU_ICG_APB_ENA_UART0 6
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#define PMU_ICG_APB_ENA_UART1 7
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#define PMU_ICG_APB_ENA_UHCI 8
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#define PMU_ICG_APB_ENA_SARADC 9
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#define PMU_ICG_APB_ENA_TG0 11
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#define PMU_ICG_APB_ENA_TG1 12
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#define PMU_ICG_APB_ENA_I2C 13
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#define PMU_ICG_APB_ENA_LEDC 14
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#define PMU_ICG_APB_ENA_RMT 15
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#define PMU_ICG_APB_ENA_SYSTIMER 16
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#define PMU_ICG_APB_ENA_USB_DEVICE 17
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#define PMU_ICG_APB_ENA_TWAI0 18
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#define PMU_ICG_APB_ENA_TWAI1 19
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#define PMU_ICG_APB_ENA_PCNT 20
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#define PMU_ICG_APB_ENA_PWM 21
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#define PMU_ICG_APB_ENA_SOC_ETM 22
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#define PMU_ICG_APB_ENA_PARL 23
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#define PMU_ICG_APB_ENA_REGDMA 24
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#define PMU_ICG_APB_ENA_MEM_MONITOR 25
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#define PMU_ICG_APB_ENA_IOMUX 26
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#define PMU_ICG_APB_ENA_PVT_MONITOR 27
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#define PMU_ICG_FUNC_ENA_GDMA 0
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#define PMU_ICG_FUNC_ENA_SPI2 1
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#define PMU_ICG_FUNC_ENA_I2S_RX 2
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#define PMU_ICG_FUNC_ENA_UART0 3
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#define PMU_ICG_FUNC_ENA_UART1 4
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#define PMU_ICG_FUNC_ENA_UHCI 5
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#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
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#define PMU_ICG_FUNC_ENA_I2S_TX 7
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#define PMU_ICG_FUNC_ENA_REGDMA 8
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#define PMU_ICG_FUNC_ENA_RETENTION 9
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#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
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#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
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#define PMU_ICG_FUNC_ENA_TSENS 12
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#define PMU_ICG_FUNC_ENA_TG1 13
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#define PMU_ICG_FUNC_ENA_TG0 14
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#define PMU_ICG_FUNC_ENA_HPBUS 15
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#define PMU_ICG_FUNC_ENA_SOC_ETM 16
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#define PMU_ICG_FUNC_ENA_HPCORE 17
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#define PMU_ICG_FUNC_ENA_SYSTIMER 18
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#define PMU_ICG_FUNC_ENA_SEC 19
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#define PMU_ICG_FUNC_ENA_SARADC 20
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#define PMU_ICG_FUNC_ENA_RMT 21
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#define PMU_ICG_FUNC_ENA_PWM 22
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#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
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#define PMU_ICG_FUNC_ENA_PARL_TX 24
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#define PMU_ICG_FUNC_ENA_PARL_RX 25
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#define PMU_ICG_FUNC_ENA_MSPI 26
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#define PMU_ICG_FUNC_ENA_LEDC 27
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#define PMU_ICG_FUNC_ENA_IOMUX 28
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#define PMU_ICG_FUNC_ENA_I2C 29
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#define PMU_ICG_FUNC_ENA_TWAI1 30
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#define PMU_ICG_FUNC_ENA_TWAI0 31
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#define DR_REG_TRACE0_BASE 0x60000000
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#define DR_REG_TRACE1_BASE 0x60001000
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#define DR_REG_ASSIST_DEBUG_BASE 0x60002000
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#define DR_REG_INTPRI_BASE 0x60005000
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#define DR_REG_CACHE_BASE 0x60008000
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#define DR_REG_GPSPI2_BASE 0x60010000
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#define DR_REG_GPSPI3_BASE 0x60011000
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#define DR_REG_UART0_BASE 0x60012000
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#define DR_REG_UART1_BASE 0x60013000
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#define DR_REG_UHCI0_BASE 0x60014000
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#define DR_REG_I2C0_BASE 0x60015000
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#define DR_REG_I2C1_BASE 0x60016000
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#define DR_REG_I2S0_BASE 0x60017000
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#define DR_REG_PARL_IO_BASE 0x60018000
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#define DR_REG_MCPWM0_BASE 0x60019000
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#define DR_REG_MCPWM1_BASE 0x6001A000
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#define DR_REG_LEDC_BASE 0x6001B000
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#define DR_REG_TWAIFD_BASE 0x6001C000
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#define DR_REG_USB_SERIAL_JTAG_BASE 0x6001D000
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#define DR_REG_RMT_BASE 0x6001E000
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#define DR_REG_AHB_DMA_BASE 0x6001F000
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#define DR_REG_PAU_BASE 0x60020000
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#define DR_REG_SOC_ETM_BASE 0x60021000
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#define DR_REG_APB_SARADC_BASE 0x60022000
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#define DR_REG_SYSTIMER_BASE 0x60023000
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#define DR_REG_MEM_MONITOR_BASE 0x60025000
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#define DR_REG_PVT_BASE 0x60026000
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#define DR_REG_PCNT_BASE 0x60027000
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#define DR_REG_SAMPLE_RATE_CONVERTER_BASE 0x60028000
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#define DR_REG_ZERO_DET_BASE 0x60029000
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#define DR_REG_USB_OTG_FS_CORE0_BASE 0x60040000
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#define DR_REG_USB_OTG_FS_CORE1_BASE 0x6007F000
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#define DR_REG_USB_OTG_FS_PHY_BASE 0x60080000
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#define DR_REG_TIMERG0_BASE 0x60090000
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#define DR_REG_TIMERG1_BASE 0x60091000
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#define DR_REG_IO_MUX_BASE 0x60092000
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#define DR_REG_GPIO_BASE 0x60093000
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#define DR_REG_GPIO_EXT_BASE 0x60093E00
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#define DR_REG_PCR_BASE 0x60094000
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#define DR_REG_SPIMEM0_BASE 0x60098000
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#define DR_REG_SPIMEM1_BASE 0x60099000
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#define DR_REG_INTMTX0_BASE 0x6009A000
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#define DR_REG_INTMTX1_BASE 0x6009B000
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#define DR_REG_HP_SYSTEM_BASE 0x6009C000
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#define DR_REG_HP_APM_BASE 0x6009D000
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#define DR_REG_CPU_APM_REG_BASE 0x6009E000
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#define DR_REG_TEE_BASE 0x6009F000
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#define DR_REG_KEYMNG_BASE 0x600A5000
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#define DR_REG_AES_BASE 0x600A6000
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#define DR_REG_SHA_BASE 0x600A7000
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#define DR_REG_ECC_BASE 0x600A8000
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#define DR_REG_HMAC_BASE 0x600A9000
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#define DR_REG_ECDSA_BASE 0x600AA000
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#define DR_REG_HUK_BASE 0x600B1000
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#define DR_REG_LP_TEE_BASE 0x600B1400
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#define DR_REG_EFUSE_BASE 0x600B1800
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#define DR_REG_OTP_DEBUG_BASE 0x600B1C00
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#define DR_REG_TRNG_BASE 0x600B2000
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#define DR_REG_PMU_BASE 0x600B2400
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#define DR_REG_LP_AON_BASE 0x600B2800
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#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00
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#define DR_REG_LP_CLKRST_BASE 0x600B3000
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#define DR_REG_LPPERI_BASE 0x600B3400
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#define DR_REG_LP_IO_MUX_BASE 0x600B3800
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#define DR_REG_LP_GPIO_BASE 0x600B3C00
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#define DR_REG_LP_TIMER_BASE 0x600B5000
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#define DR_REG_LP_WDT_BASE 0x600B5400
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#define DR_REG_TOUCH_SENS_BASE 0x600B5800
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#define DR_REG_TOUCH_AON_BASE 0x600B5C00
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#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 // TODO: [ESP32H4] IDF-12315 inherit from verify code, need check

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