Skip to content

Commit 377f7ad

Browse files
esp-lisesp-lis
committed
change(esp_hw_support): enable wifi beacon wakeup and support wifi modem state for esp32c61
1 parent 76920d1 commit 377f7ad

File tree

3 files changed

+125
-3
lines changed

3 files changed

+125
-3
lines changed

‎components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c‎

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include "soc/soc_caps.h"
7+
#include "soc/i2c_ana_mst_reg.h"
8+
#include "soc/pmu_reg.h"
9+
10+
#include "modem/modem_syscon_reg.h"
11+
#include "modem/modem_lpcon_reg.h"
12+
13+
#include "esp_private/esp_pau.h"
14+
#include "esp_private/sleep_modem.h"
15+
#include "esp_private/sleep_retention.h"
16+
17+
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
18+
19+
#define SARADC_TSENS_REG (0x6000e058)
20+
#define SARADC_TSENS_PU (BIT(22))
21+
#define PMU_RF_PWR_REG (0x600b0158)
22+
23+
#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a001c)
24+
#define FECOEX_SET_CHAN_EN (BIT(17))
25+
#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
26+
#define FECOEX_SET_CHAN_DONE (BIT(8))
27+
#define FECOEX_AGC_CONF_REG (0x600a7030)
28+
#define FECOEX_AGC_DIS (BIT(29))
29+
30+
#define WDEVTXQ_BLOCK (0x600a4ca8)
31+
#define WDEV_RXBLOCK (BIT(12))
32+
33+
esp_err_t sleep_modem_state_phy_link_init(void **link_head)
34+
{
35+
esp_err_t err = ESP_OK;
36+
37+
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
38+
static regdma_link_config_t wifi_modem_config[] = {
39+
[0] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), /* I2C MST enable */
40+
41+
/* PMU or software to trigger enable RF PHY */
42+
[1] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), /* BBPLL calibration enable */
43+
[2] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf0000000, 0xf0000000, 1, 0),
44+
[3] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0),
45+
46+
[4] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0),
47+
[5] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
48+
[6] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x06), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
49+
[7] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
50+
51+
[8] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0),
52+
[9] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0),
53+
[10] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), PMU_DATE_REG, ~FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
54+
[11] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0b), PMU_DATE_REG, ~FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
55+
[12] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
56+
[13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0),
57+
[14] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0),
58+
59+
/* PMU to trigger enable RXBLOCK */
60+
[15] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0),
61+
62+
/* PMU or software to trigger disable RF PHY */
63+
[16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1),
64+
[17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1),
65+
[18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 0, 1),
66+
[19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 0, 1),
67+
[20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
68+
[21] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
69+
[22] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
70+
[23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x17), SARADC_TSENS_REG, 0, 0x400000, 0, 1),
71+
[24] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_RF_PWR_REG, 0, 0xf0000000, 0, 1),
72+
[25] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), /* BBPLL calibration disable */
73+
74+
[26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), /* I2C MST disable */
75+
76+
/* PMU to trigger disable RXBLOCK */
77+
[27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), PMU_DATE_REG, ~0, 0x6000, 0, 1),
78+
[28] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1c), PMU_DATE_REG, ~0, 0x6000, 0, 1),
79+
[29] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1),
80+
[30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1),
81+
[31] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), PMU_DATE_REG, ~0, 0x6000, 0, 1),
82+
[32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x20), PMU_DATE_REG, ~0, 0x6000, 0, 1),
83+
[33] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1),
84+
85+
[34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x22), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0),
86+
[35] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1)
87+
};
88+
extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
89+
wifi_modem_config[4].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
90+
wifi_modem_config[19].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
91+
92+
void *link = NULL;
93+
for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
94+
void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
95+
if (next) {
96+
link = next;
97+
} else {
98+
regdma_link_destroy(link, 0);
99+
err = ESP_ERR_NO_MEM;
100+
}
101+
}
102+
if (err == ESP_OK) {
103+
pau_regdma_set_modem_link_addr(link);
104+
*link_head = link;
105+
}
106+
#endif
107+
return err;
108+
}
109+
110+
esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
111+
{
112+
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
113+
regdma_link_destroy(link_head, 0);
114+
#endif
115+
return ESP_OK;
116+
}
117+
118+
#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

‎components/soc/esp32c61/include/soc/Kconfig.soc_caps.in‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -815,6 +815,10 @@ config SOC_PM_SUPPORT_WIFI_WAKEUP
815815
bool
816816
default y
817817

818+
config SOC_PM_SUPPORT_BEACON_WAKEUP
819+
bool
820+
default y
821+
818822
config SOC_PM_SUPPORT_EXT1_WAKEUP
819823
bool
820824
default y
@@ -865,7 +869,7 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
865869

866870
config SOC_PM_SUPPORT_PMU_MODEM_STATE
867871
bool
868-
default n
872+
default y
869873

870874
config SOC_PM_CPU_RETENTION_BY_SW
871875
bool

‎components/soc/esp32c61/include/soc/soc_caps.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -415,7 +415,7 @@
415415
// TODO: IDF-5351 (Copy from esp32c3, need check)
416416
/*-------------------------- Power Management CAPS ----------------------------*/
417417
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
418-
// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
418+
#define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
419419
// #define SOC_PM_SUPPORT_BT_WAKEUP (1)
420420
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
421421
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
@@ -430,7 +430,7 @@
430430
#define SOC_PM_SUPPORT_MAC_BB_PD (1)
431431
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
432432

433-
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (0)
433+
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
434434
/* macro redefine for pass esp_wifi headers md5sum check */
435435
#define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
436436

0 commit comments

Comments
 (0)