feat(uart): support uart sleep retention on C5/C61

Author: songruo

components/esp_driver_uart/src/uart.c

@@ -170,10 +170,6 @@ typedef struct {
     uart_hal_context_t hal;        /*!< UART hal context*/
     DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(spinlock)
     bool hw_enabled;
-#if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
-    bool retention_link_inited;    /*!< Mark whether the retention link is inited */
-    bool retention_link_created;   /*!< Mark whether the retention link is created */
-#endif
 } uart_context_t;
 
 static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
@@ -197,7 +193,7 @@ static uart_context_t uart_context[UART_NUM_MAX] = {
 
 static portMUX_TYPE uart_selectlock = portMUX_INITIALIZER_UNLOCKED;
 
-#if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
 static esp_err_t uart_create_sleep_retention_link_cb(void *arg);
 #endif
 
@@ -218,11 +214,11 @@ static void uart_module_enable(uart_port_t uart_num)
                 }
             }
 
-#if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP // for targets that is !SOC_UART_SUPPORT_SLEEP_RETENTION, retention module should still be inited to avoid TOP PD
             // Initialize sleep retention module for HP UART
             if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { // Console uart retention has been taken care in sleep_sys_periph_stdout_console_uart_retention_init
-                assert(!uart_context[uart_num].retention_link_inited);
                 sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
+                assert(!sleep_retention_is_module_inited(module));
                 sleep_retention_module_init_param_t init_param = {
                     .cbs = {
                         .create = {
@@ -232,9 +228,7 @@ static void uart_module_enable(uart_port_t uart_num)
                     },
                     .depends = RETENTION_MODULE_BITMAP_INIT(CLOCK_SYSTEM)
                 };
-                if (sleep_retention_module_init(module, &init_param) == ESP_OK) {
-                    uart_context[uart_num].retention_link_inited = true;
-                } else {
+                if (sleep_retention_module_init(module, &init_param) != ESP_OK) {
                     ESP_LOGW(UART_TAG, "init sleep retention failed for uart%d, power domain may be turned off during sleep", uart_num);
                 }
             }
@@ -259,13 +253,12 @@ static void uart_module_disable(uart_port_t uart_num)
     _lock_acquire(&(uart_context[uart_num].mutex));
     if (uart_context[uart_num].hw_enabled != false) {
         if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
-#if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
             // Uninitialize sleep retention module for HP UART
             sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
-            assert(!uart_context[uart_num].retention_link_created); // HP UART sleep retention should have been freed at this moment
-            if (uart_context[uart_num].retention_link_inited) {
+            assert(!sleep_retention_is_module_created(module)); // HP UART sleep retention should have been freed at this moment
+            if (sleep_retention_is_module_inited(module)) {
                 sleep_retention_module_deinit(module);
-                uart_context[uart_num].retention_link_inited = false;
             }
 #endif
             HP_UART_SRC_CLK_ATOMIC() {
@@ -888,21 +881,18 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
     if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
         _lock_acquire(&(uart_context[uart_num].mutex));
         sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
-        if (allow_pd && !uart_context[uart_num].retention_link_created) {
-            if (uart_context[uart_num].retention_link_inited) {
-                if (sleep_retention_module_allocate(module) == ESP_OK) {
-                    uart_context[uart_num].retention_link_created = true;
-                } else {
+        if (allow_pd && !sleep_retention_is_module_created(module)) {
+            if (sleep_retention_is_module_inited(module)) {
+                if (sleep_retention_module_allocate(module) != ESP_OK) {
                     // Even though the sleep retention module create failed, UART driver should still work, so just warning here
                     ESP_LOGW(UART_TAG, "create retention module failed, power domain can't turn off");
                 }
             } else {
                 ESP_LOGW(UART_TAG, "retention module not initialized first, unable to create retention module");
             }
-        } else if (!allow_pd && uart_context[uart_num].retention_link_created) {
-            assert(uart_context[uart_num].retention_link_inited);
+        } else if (!allow_pd && sleep_retention_is_module_created(module)) {
+            assert(sleep_retention_is_module_inited(module));
             sleep_retention_module_free(module);
-            uart_context[uart_num].retention_link_created = false;
         }
         _lock_release(&(uart_context[uart_num].mutex));
     }
@@ -1831,10 +1821,9 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
     if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
         sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
         _lock_acquire(&(uart_context[uart_num].mutex));
-        if (uart_context[uart_num].retention_link_created) {
-            assert(uart_context[uart_num].retention_link_inited);
+        if (sleep_retention_is_module_created(module)) {
+            assert(sleep_retention_is_module_inited(module));
             sleep_retention_module_free(module);
-            uart_context[uart_num].retention_link_created = false;
         }
         _lock_release(&(uart_context[uart_num].mutex));
     }
@@ -1998,16 +1987,18 @@ void uart_set_always_rx_timeout(uart_port_t uart_num, bool always_rx_timeout)
     }
 }
 
-#if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
 static esp_err_t uart_create_sleep_retention_link_cb(void *arg)
 {
+#if SOC_UART_SUPPORT_SLEEP_RETENTION
     uart_context_t *group = (uart_context_t *)arg;
     uart_port_t uart_num = group->port_id;
     sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
     esp_err_t err = sleep_retention_entries_create(uart_reg_retention_info[uart_num].regdma_entry_array,
                                                    uart_reg_retention_info[uart_num].array_size,
                                                    REGDMA_LINK_PRI_UART, module);
     ESP_RETURN_ON_ERROR(err, UART_TAG, "create retention link failed");
+#endif
     return ESP_OK;
 }
 #endif

components/esp_hw_support/sleep_system_peripheral.c

@@ -182,7 +182,7 @@ bool peripheral_domain_pd_allowed(void)
 #if SOC_UART_SUPPORT_SLEEP_RETENTION
     mask.bitmap[SLEEP_RETENTION_MODULE_UART0 >> 5] |= BIT(SLEEP_RETENTION_MODULE_UART0 % 32);
     mask.bitmap[SLEEP_RETENTION_MODULE_UART1 >> 5] |= BIT(SLEEP_RETENTION_MODULE_UART1 % 32);
-# if (SOC_UART_HP_NUM > 2) && !CONFIG_IDF_TARGET_ESP32C61   // TODO: IDF-11370
+# if (SOC_UART_HP_NUM > 2)
     mask.bitmap[SLEEP_RETENTION_MODULE_UART2 >> 5] |= BIT(SLEEP_RETENTION_MODULE_UART2 % 32);
 # endif
 # if (SOC_UART_HP_NUM > 3)

components/soc/esp32c5/register/soc/lp_uart_reg.h

@@ -1287,6 +1287,27 @@ extern "C" {
  *  LP UART core clock configuration
  */
 #define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
+/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor.
+ */
+#define LP_UART_SCLK_DIV_B    0x0000003FU
+#define LP_UART_SCLK_DIV_B_M  (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S)
+#define LP_UART_SCLK_DIV_B_V  0x0000003FU
+#define LP_UART_SCLK_DIV_B_S  0
+/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor.
+ */
+#define LP_UART_SCLK_DIV_A    0x0000003FU
+#define LP_UART_SCLK_DIV_A_M  (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S)
+#define LP_UART_SCLK_DIV_A_V  0x0000003FU
+#define LP_UART_SCLK_DIV_A_S  6
+/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
+ *  The integral part of the frequency divider factor.
+ */
+#define LP_UART_SCLK_DIV_NUM    0x000000FFU
+#define LP_UART_SCLK_DIV_NUM_M  (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S)
+#define LP_UART_SCLK_DIV_NUM_V  0x000000FFU
+#define LP_UART_SCLK_DIV_NUM_S  12
 /** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
  *  Configures whether or not to enable LP UART TX clock.\\
  *  0: Disable\\

components/soc/esp32c5/register/soc/uart_struct.h

@@ -16,7 +16,7 @@ extern "C" {
  */
 typedef union {
     struct {
-        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
          *  Represents the data UART $n read from FIFO.\\
          *  Measurement unit: byte.
          */
@@ -950,17 +950,17 @@ typedef union {
          *  The  denominator of the frequency divider factor.'
          *  Only available to LP UART instance
          */
-        uint32_t sclk_div_b:6;
+        uint32_t sclk_div_b:6;                                      /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
         /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
          *  The numerator of the frequency divider factor.
          *  Only available to LP UART instance
          */
-        uint32_t sclk_div_a:6;
+        uint32_t sclk_div_a:6;                                      /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
         /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
          *  The integral part of the frequency divider factor.
          *  Only available to LP UART instance
          */
-        uint32_t sclk_div_num:8;
+        uint32_t sclk_div_num:8;                                    /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
         uint32_t reserved_20:4;
         /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
          *  Configures whether or not to enable UART TX clock.\\
@@ -1308,7 +1308,7 @@ typedef union {
 } uart_id_reg_t;
 
 
-typedef struct {
+typedef struct uart_dev_s {
     volatile uart_fifo_reg_t fifo;
     volatile uart_int_raw_reg_t int_raw;
     volatile uart_int_st_reg_t int_st;

components/soc/esp32c6/register/soc/lp_uart_reg.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -1256,27 +1256,6 @@ extern "C" {
 #define LP_UART_SCLK_DIV_NUM_M  (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S)
 #define LP_UART_SCLK_DIV_NUM_V  0x000000FFU
 #define LP_UART_SCLK_DIV_NUM_S  12
-/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
- */
-#define LP_UART_SCLK_SEL    0x00000003U
-#define LP_UART_SCLK_SEL_M  (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S)
-#define LP_UART_SCLK_SEL_V  0x00000003U
-#define LP_UART_SCLK_SEL_S  20
-/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set this bit to enable UART Tx/Rx clock.
- */
-#define LP_UART_SCLK_EN    (BIT(22))
-#define LP_UART_SCLK_EN_M  (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S)
-#define LP_UART_SCLK_EN_V  0x00000001U
-#define LP_UART_SCLK_EN_S  22
-/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
- */
-#define LP_UART_RST_CORE    (BIT(23))
-#define LP_UART_RST_CORE_M  (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S)
-#define LP_UART_RST_CORE_V  0x00000001U
-#define LP_UART_RST_CORE_S  23
 /** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
  *  Set this bit to enable UART Tx clock.
  */

components/soc/esp32c6/register/soc/uart_reg.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -1471,6 +1471,39 @@ extern "C" {
 #define UART_RXD_EDGE_CNT_V  0x000003FFU
 #define UART_RXD_EDGE_CNT_S  0
 
+/** UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
+/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
+#define UART_TX_SCLK_EN_V  0x00000001U
+#define UART_TX_SCLK_EN_S  24
+/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
+#define UART_RX_SCLK_EN_V  0x00000001U
+#define UART_RX_SCLK_EN_S  25
+/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx.
+ */
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
+#define UART_TX_RST_CORE_V  0x00000001U
+#define UART_TX_RST_CORE_S  26
+/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Rx.
+ */
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
+#define UART_RX_RST_CORE_V  0x00000001U
+#define UART_RX_RST_CORE_S  27
+
 /** UART_DATE_REG register
  *  UART Version register
  */

components/soc/esp32c6/register/soc/uart_struct.h

@@ -883,27 +883,16 @@ typedef union {
         /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
          *  The  denominator of the frequency divider factor.
          */
-        uint32_t sclk_div_b:6;
+        uint32_t sclk_div_b:6;                                      /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
         /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
          *  The numerator of the frequency divider factor.
          */
-        uint32_t sclk_div_a:6;
+        uint32_t sclk_div_a:6;                                      /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
         /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
          *  The integral part of the frequency divider factor.
          */
-        uint32_t sclk_div_num:8;
-        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
-         */
-        uint32_t sclk_sel:2;
-        /** sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set this bit to enable UART Tx/Rx clock.
-         */
-        uint32_t sclk_en:1;
-        /** rst_core : R/W; bitpos: [23]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
-         */
-        uint32_t rst_core:1;
+        uint32_t sclk_div_num:8;                                    /* UART0/1 instance have this field reserved, configure in corresponding PCR registers */
+        uint32_t reserved_20:4;
         /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
          *  Set this bit to enable UART Tx clock.
          */
@@ -1273,7 +1262,7 @@ typedef struct uart_dev_s {
     volatile uart_lowpulse_reg_t lowpulse;      /* LP_UART instance has this register reserved */
     volatile uart_highpulse_reg_t highpulse;    /* LP_UART instance has this register reserved */
     volatile uart_rxd_cnt_reg_t rxd_cnt;        /* LP_UART instance has this register reserved */
-    volatile uart_clk_conf_reg_t clk_conf;      /* UART0/1 instance have this register reserved, configure in corresponding PCR registers */
+    volatile uart_clk_conf_reg_t clk_conf;
     volatile uart_date_reg_t date;
     volatile uart_afifo_status_reg_t afifo_status;
     uint32_t reserved_094;

components/soc/esp32c6/uart_periph.c

@@ -124,11 +124,11 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
  * UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG,
  * UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG,
  * UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG,
- * UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_ID_REG
+ * UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_CLK_CONF_REG, UART_ID_REG
  */
-#define UART_RETENTION_ADDR_MAP_REGS_CNT 21
+#define UART_RETENTION_ADDR_MAP_REGS_CNT 22
 #define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i)
-static const uint32_t uart_regs_map[4] = {0x7fff6d, 0x10, 0x0, 0x0};
+static const uint32_t uart_regs_map[4] = {0x807fff6d, 0x10, 0x0, 0x0};
 #define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
     [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \
                                                UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \

components/soc/esp32c61/include/soc/retention_periph_defs.h

@@ -34,11 +34,12 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_I2C0         = 12,
     SLEEP_RETENTION_MODULE_UART0        = 14,
     SLEEP_RETENTION_MODULE_UART1        = 15,
-    SLEEP_RETENTION_MODULE_ETM0         = 16,
-    SLEEP_RETENTION_MODULE_GPSPI2       = 17,
-    SLEEP_RETENTION_MODULE_LEDC         = 18,
-    SLEEP_RETENTION_MODULE_I2S0         = 19,
-    SLEEP_RETENTION_MODULE_TEMP_SENSOR  = 20,
+    SLEEP_RETENTION_MODULE_UART2        = 16,
+    SLEEP_RETENTION_MODULE_ETM0         = 17,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 18,
+    SLEEP_RETENTION_MODULE_LEDC         = 19,
+    SLEEP_RETENTION_MODULE_I2S0         = 20,
+    SLEEP_RETENTION_MODULE_TEMP_SENSOR  = 21,
 
     /* Modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
@@ -63,6 +64,7 @@ typedef enum periph_retention_module {
     : ((m) == SLEEP_RETENTION_MODULE_I2C0)         ? true \
     : ((m) == SLEEP_RETENTION_MODULE_UART0)        ? true \
     : ((m) == SLEEP_RETENTION_MODULE_UART1)        ? true \
+    : ((m) == SLEEP_RETENTION_MODULE_UART2)        ? true \
     : ((m) == SLEEP_RETENTION_MODULE_ETM0)         ? true \
     : ((m) == SLEEP_RETENTION_MODULE_GPSPI2)       ? true \
     : ((m) == SLEEP_RETENTION_MODULE_LEDC)         ? true \

components/soc/esp32c61/include/soc/soc_caps.h

@@ -407,7 +407,8 @@
 #define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */
 #define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
 #define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
-#define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)
+#define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)      /*!< Support back up registers before sleep */
+
 // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)