refactor(i2c): rename some LL functions according to TRM descriptions

Author: suda-morris

components/driver/i2c/i2c.c

@@ -810,7 +810,7 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
 #if SOC_I2C_SUPPORT_SLAVE
     if (i2c_conf->mode == I2C_MODE_SLAVE) {  //slave mode
         i2c_hal_slave_init(&(i2c_context[i2c_num].hal));
-        i2c_ll_slave_tx_auto_start_en(i2c_context[i2c_num].hal.dev, true);
+        i2c_ll_slave_enable_auto_start(i2c_context[i2c_num].hal.dev, true);
         I2C_CLOCK_SRC_ATOMIC() {
             i2c_ll_set_source_clk(i2c_context[i2c_num].hal.dev, src_clk);
         }
@@ -1504,7 +1504,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t
         }
     }
     i2c_ll_update(i2c_context[i2c_num].hal.dev);
-    i2c_ll_master_trans_start(i2c_context[i2c_num].hal.dev);
+    i2c_ll_start_trans(i2c_context[i2c_num].hal.dev);
     return;
 }
 

components/esp_driver_i2c/i2c_master.c

@@ -130,6 +130,7 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
     }
 
     i2c_hal_master_init(hal);
+    i2c_ll_enable_fifo_mode(hal->dev, true);
     i2c_ll_disable_intr_mask(hal->dev, I2C_LL_INTR_MASK);
     i2c_ll_clear_intr_mask(hal->dev, I2C_LL_INTR_MASK);
     i2c_hal_set_timing_config(hal, &timing_config);

components/esp_driver_i2c/i2c_slave.c

@@ -247,11 +247,11 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
 
 #if SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
     if (i2c_slave->fifo_mode == I2C_SLAVE_NONFIFO) {
-        i2c_ll_slave_set_fifo_mode(hal->dev, false);
-        i2c_ll_enable_mem_access_nonfifo(hal->dev, true);
+        i2c_ll_enable_fifo_mode(hal->dev, false);
+        i2c_ll_slave_enable_dual_addressing_mode(hal->dev, true);
     } else {
-        i2c_ll_slave_set_fifo_mode(hal->dev, true);
-        i2c_ll_enable_mem_access_nonfifo(hal->dev, false);
+        i2c_ll_enable_fifo_mode(hal->dev, true);
+        i2c_ll_slave_enable_dual_addressing_mode(hal->dev, false);
     }
 #endif
 
@@ -273,7 +273,7 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
 #if SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     i2c_ll_slave_enable_scl_stretch(hal->dev, slave_config->flags.stretch_en);
 #endif
-    i2c_ll_slave_tx_auto_start_en(hal->dev, true);
+    i2c_ll_slave_enable_auto_start(hal->dev, true);
 
     i2c_ll_update(hal->dev);
     portEXIT_CRITICAL(&i2c_slave->base->spinlock);
@@ -386,7 +386,7 @@ esp_err_t i2c_slave_read_ram(i2c_slave_dev_handle_t i2c_slave, uint8_t ram_offse
         portEXIT_CRITICAL(&i2c_slave->base->spinlock);
         return ESP_ERR_INVALID_SIZE;
     }
-    i2c_ll_read_by_nonfifo(hal->dev, ram_offset, data, fifo_size);
+    i2c_ll_read_rx_by_nonfifo(hal->dev, ram_offset, data, fifo_size);
     portEXIT_CRITICAL(&i2c_slave->base->spinlock);
 
     return ESP_OK;
@@ -407,7 +407,7 @@ esp_err_t i2c_slave_write_ram(i2c_slave_dev_handle_t i2c_slave, uint8_t ram_offs
         ESP_EARLY_LOGE(TAG, "No extra fifo to fill your buffer, please split your buffer");
         return ESP_ERR_INVALID_SIZE;
     }
-    i2c_ll_write_by_nonfifo(hal->dev, ram_offset, data, size);
+    i2c_ll_write_tx_by_nonfifo(hal->dev, ram_offset, data, size);
     xSemaphoreGive(i2c_slave->slv_tx_mux);
     return ESP_OK;
 }

components/esp_driver_i2c/i2c_slave_v2.c

@@ -290,7 +290,7 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
 
     portENTER_CRITICAL(&i2c_slave->base->spinlock);
     i2c_hal_slave_init(hal);
-    i2c_ll_slave_set_fifo_mode(hal->dev, true);
+    i2c_ll_enable_fifo_mode(hal->dev, true);
     i2c_ll_set_slave_addr(hal->dev, slave_config->slave_addr, false);
     i2c_ll_set_tout(hal->dev, I2C_LL_MAX_TIMEOUT);
 

components/hal/esp32/include/hal/i2c_ll.h

@@ -280,7 +280,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
  *
  * @return None
  */
-static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
+static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
 {
     hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
 }
@@ -299,7 +299,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
 }
 
 /**
- * @brief  Configure I2C slave broadcasting mode.
+ * @brief  Enable the I2C slave to respond to broadcast address
  *
  * @param  hw Beginning address of the peripheral registers
  * @param  broadcast_en Set true to enable broadcast, else, set it false
@@ -509,7 +509,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
  * @return None
  */
 __attribute__((always_inline))
-static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
+static inline void i2c_ll_start_trans(i2c_dev_t *hw)
 {
     hw->ctr.trans_start = 1;
 }
@@ -708,7 +708,6 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
     ctrl_reg.sda_force_out = 1;
     ctrl_reg.scl_force_out = 1;
     hw->ctr.val = ctrl_reg.val;
-    hw->fifo_conf.fifo_addr_cfg_en = 0;
 }
 
 /**
@@ -770,12 +769,12 @@ static inline void i2c_ll_reset_register(int i2c_port)
 #define i2c_ll_reset_register(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; i2c_ll_reset_register(__VA_ARGS__);} while(0)
 
 /**
- * @brief Set whether slave should auto start, or only start with start signal from master
+ * @brief Enable I2C slave to automatically send data when addressed by the master
  *
  * @param hw Beginning address of the peripheral registers
  * @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
  */
-static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
+static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
 {
     ;// ESP32 do not support
 }

components/hal/esp32c2/include/hal/i2c_ll.h

@@ -76,7 +76,7 @@ typedef enum {
  */
 static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal)
 {
-    uint32_t clkm_div = source_clk / (bus_freq * 1024) +1;
+    uint32_t clkm_div = source_clk / (bus_freq * 1024) + 1;
     uint32_t sclk_freq = source_clk / clkm_div;
     uint32_t half_cycle = sclk_freq / bus_freq / 2;
     //SCL
@@ -85,7 +85,7 @@ static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_f
     // default, scl_wait_high < scl_high
     // Make 80KHz as a boundary here, because when working at lower frequency, too much scl_wait_high will faster the frequency
     // according to some hardware behaviors.
-    clk_cal->scl_wait_high = (bus_freq >= 80*1000) ? (half_cycle / 2 - 2) : (half_cycle / 4);
+    clk_cal->scl_wait_high = (bus_freq >= 80 * 1000) ? (half_cycle / 2 - 2) : (half_cycle / 4);
     clk_cal->scl_high = half_cycle - clk_cal->scl_wait_high;
     clk_cal->sda_hold = half_cycle / 4;
     clk_cal->sda_sample = half_cycle / 2;
@@ -326,7 +326,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
  *
  * @return None
  */
-static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
+static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
 {
     hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
 }
@@ -414,6 +414,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
  */
 static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 {
+    hw->fifo_conf.fifo_prt_en = 1;
     hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
 }
 
@@ -427,6 +428,8 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
  */
 static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
 {
+    hw->fifo_conf.fifo_prt_en = 1;
+    hw->ctr.rx_full_ack_level = 0;
     hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
 }
 
@@ -543,7 +546,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
  * @return None
  */
 __attribute__((always_inline))
-static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
+static inline void i2c_ll_start_trans(i2c_dev_t *hw)
 {
     hw->ctr.trans_start = 1;
 }
@@ -590,8 +593,8 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
 __attribute__((always_inline))
 static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
 {
-    for (int i = 0; i< len; i++) {
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
+    for (int i = 0; i < len; i++) {
+        hw->data.val = ptr[i];
     }
 }
 
@@ -607,7 +610,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_
 __attribute__((always_inline))
 static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
-    for(int i = 0; i < len; i++) {
+    for (int i = 0; i < len; i++) {
         ptr[i] = HAL_FORCE_READ_U32_REG_FIELD(hw->data, fifo_rdata);
     }
 }

components/hal/esp32c3/include/hal/i2c_ll.h

@@ -342,7 +342,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
  *
  * @return None
  */
-static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
+static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
 {
     hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
 }
@@ -361,7 +361,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
 }
 
 /**
- * @brief  Configure I2C slave broadcasting mode.
+ * @brief  Enable the I2C slave to respond to broadcast address
  *
  * @param  hw Beginning address of the peripheral registers
  * @param  broadcast_en Set true to enable broadcast, else, set it false
@@ -495,6 +495,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
  */
 static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 {
+    hw->fifo_conf.fifo_prt_en = 1;
     hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr;
 }
 
@@ -509,6 +510,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
 {
     hw->fifo_conf.fifo_prt_en = 1;
+    hw->ctr.rx_full_ack_level = 0;
     hw->fifo_conf.rx_fifo_wm_thrhd = full_thr;
 }
 
@@ -625,7 +627,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
  * @return None
  */
 __attribute__((always_inline))
-static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
+static inline void i2c_ll_start_trans(i2c_dev_t *hw)
 {
     hw->ctr.trans_start = 1;
 }
@@ -673,7 +675,7 @@ __attribute__((always_inline))
 static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
 {
     for (int i = 0; i < len; i++) {
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->fifo_data, data, ptr[i]);
+        hw->fifo_data.val = ptr[i];
     }
 }
 
@@ -695,44 +697,46 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 }
 
 /**
- * @brief  Write the I2C hardware txFIFO
+ * @brief  Write to the TX RAM by direct address
  *
  * @param  hw Beginning address of the peripheral registers
  * @param  ram_offset Offset value of I2C RAM.
  * @param  ptr Pointer to data buffer
  * @param  len Amount of data needs to be written
  */
-static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
+static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
 {
     for (int i = 0; i < len; i++) {
         hw->txfifo_mem[i + ram_offset] = ptr[i];
     }
 }
 
 /**
- * @brief  Read the I2C hardware ram
+ * @brief  Read from the RX RAM by direct address
  *
  * @param  hw Beginning address of the peripheral registers
  * @param  ram_offset Offset value of I2C RAM.
  * @param  ptr Pointer to data buffer
  * @param  len Amount of data needs read
  */
-static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
+static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
 {
     for (int i = 0; i < len; i++) {
         ptr[i] = hw->rxfifo_mem[i + ram_offset];
     }
 }
 
 /**
- * @brief Get access to I2C RAM address directly
+ * @brief Enable I2C slave dual addressing mode
+ *
+ * @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
  *
  * @param  hw Beginning address of the peripheral registers
  * @param  addr_wr_en Enable I2C ram address read and write
  *
  * @return None
 */
-static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
+static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
 {
     hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
 }
@@ -874,16 +878,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
     ctrl_reg.sda_force_out = 1;
     ctrl_reg.scl_force_out = 1;
     hw->ctr.val = ctrl_reg.val;
-    hw->fifo_conf.fifo_addr_cfg_en = 0;
 }
 
 /**
- * @brief Set whether slave should auto start, or only start with start signal from master
+ * @brief Enable I2C slave to automatically send data when addressed by the master
  *
  * @param hw Beginning address of the peripheral registers
  * @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
  */
-static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
+static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
 {
     hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
 }