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Merge branch 'test/flash_suspend_test_framework' into 'master'
test(spi_flash): Add framework for flash suspend and allow non-necessary iram part move to flash See merge request espressif/esp-idf!35605
2 parents b88f30a + 4acf7c2 commit 4f9f6bb

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-18
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21 files changed

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‎components/esp_driver_i2c/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ menu "ESP-Driver:I2C Configurations"
22
depends on SOC_I2C_SUPPORTED
33
config I2C_ISR_IRAM_SAFE
44
bool "I2C ISR IRAM-Safe"
5+
select I2C_MASTER_ISR_HANDLER_IN_IRAM
56
default n
67
help
78
Ensure the I2C interrupt is IRAM-Safe by allowing the interrupt handler to be
@@ -23,4 +24,10 @@ menu "ESP-Driver:I2C Configurations"
2324
help
2425
I2C slave version 2 solves some existing known issues. Such as write/read workflow, stretch handling, etc.
2526

27+
config I2C_MASTER_ISR_HANDLER_IN_IRAM
28+
bool "Place I2C master ISR handler into IRAM"
29+
default y
30+
help
31+
Place I2C master ISR handler into IRAM for better performance and fewer cache misses.
32+
2633
endmenu # I2C Configurations

‎components/esp_driver_i2c/i2c_master.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -646,7 +646,7 @@ static esp_err_t s_i2c_transaction_start(i2c_master_dev_handle_t i2c_dev, int xf
646646

647647
///////////////////////////////I2C DRIVERS//////////////////////////////////////////////////////////////
648648

649-
IRAM_ATTR static void i2c_isr_receive_handler(i2c_master_bus_t *i2c_master)
649+
I2C_MASTER_ISR_ATTR static void i2c_isr_receive_handler(i2c_master_bus_t *i2c_master)
650650
{
651651
i2c_hal_context_t *hal = &i2c_master->base->hal;
652652

@@ -681,7 +681,7 @@ IRAM_ATTR static void i2c_isr_receive_handler(i2c_master_bus_t *i2c_master)
681681
#endif
682682
}
683683

684-
static void IRAM_ATTR i2c_master_isr_handler_default(void *arg)
684+
static void i2c_master_isr_handler_default(void *arg)
685685
{
686686
i2c_master_bus_handle_t i2c_master = (i2c_master_bus_t*) arg;
687687

‎components/esp_driver_i2c/i2c_private.h‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -42,6 +42,12 @@ extern "C" {
4242
#define LP_I2C_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
4343
#endif
4444

45+
#ifdef CONFIG_I2C_MASTER_ISR_HANDLER_IN_IRAM
46+
#define I2C_MASTER_ISR_ATTR IRAM_ATTR
47+
#else
48+
#define I2C_MASTER_ISR_ATTR
49+
#endif
50+
4551
#if CONFIG_I2C_ISR_IRAM_SAFE
4652
#define I2C_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
4753
#else

‎components/esp_driver_i2c/linker.lf‎

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Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
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[mapping:i2c_driver]
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archive: libesp_driver_i2c.a
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entries:
4+
if I2C_MASTER_ISR_HANDLER_IN_IRAM = y:
5+
i2c_master: i2c_master_isr_handler_default (noflash)
46
if I2C_ISR_IRAM_SAFE = y:
57
i2c_master: s_i2c_send_command_async (noflash)
68
i2c_master: s_i2c_write_command (noflash)

‎components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
1+
# SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
22
# SPDX-License-Identifier: CC0-1.0
33
import pytest
44
from pytest_embedded import Dut

‎components/hal/esp32c2/include/hal/spimem_flash_ll.h‎

Lines changed: 73 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -717,6 +717,78 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
717717
dev->user2.val = user2_reg;
718718
}
719719

720+
#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI_MEM_PES_END_INT_ENA_M
721+
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_SPI1_INTR_SOURCE
722+
723+
/**
724+
* @brief Get the address of the interrupt status register.
725+
*
726+
* This function returns a pointer to the interrupt status register of the SPI memory device.
727+
*
728+
* @param[in] dev Pointer to the SPI memory device structure.
729+
* @return volatile void* Pointer to the interrupt status register.
730+
*/
731+
static inline volatile void *spimem_flash_ll_get_interrupt_status_reg(spi_mem_dev_t *dev)
732+
{
733+
return &dev->int_st;
734+
}
735+
736+
/**
737+
* @brief Clear specific interrupt status bits.
738+
*
739+
* This function clears the specified interrupt bits in the interrupt clear register of the SPI memory device.
740+
*
741+
* @param[in] dev Pointer to the SPI memory device structure.
742+
* @param[in] mask Bitmask specifying which interrupt bits to clear.
743+
*/
744+
__attribute__((always_inline))
745+
static inline void spimem_flash_ll_clear_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
746+
{
747+
dev->int_clr.val = mask;
748+
}
749+
750+
/**
751+
* @brief Enable specific interrupt bits.
752+
*
753+
* This function enables the specified interrupts in the interrupt enable register of the SPI memory device.
754+
*
755+
* @param[in] dev Pointer to the SPI memory device structure.
756+
* @param[in] mask Bitmask specifying which interrupt bits to enable.
757+
*/
758+
__attribute__((always_inline))
759+
static inline void spimem_flash_ll_enable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
760+
{
761+
dev->int_ena.val |= mask;
762+
}
763+
764+
/**
765+
* @brief Disable specific interrupt bits.
766+
*
767+
* This function disables the specified interrupts in the interrupt enable register of the SPI memory device.
768+
*
769+
* @param[in] dev Pointer to the SPI memory device structure.
770+
* @param[in] mask Bitmask specifying which interrupt bits to disable.
771+
*/
772+
__attribute__((always_inline))
773+
static inline void spimem_flash_ll_disable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
774+
{
775+
dev->int_ena.val &= (~mask);
776+
}
777+
778+
/**
779+
* @brief Get the current interrupt status.
780+
*
781+
* This function retrieves the current interrupt status from the interrupt status register of the SPI memory device.
782+
*
783+
* @param[in] dev Pointer to the SPI memory device structure.
784+
* @param[out] intr_status Pointer to a variable where the interrupt status will be stored.
785+
*/
786+
__attribute__((always_inline))
787+
static inline void spimem_flash_ll_get_intr_mask(spi_mem_dev_t *dev, uint32_t *intr_status)
788+
{
789+
*intr_status = dev->int_st.val;
790+
}
791+
720792
#ifdef __cplusplus
721793
}
722794
#endif

‎components/hal/esp32c3/include/hal/spimem_flash_ll.h‎

Lines changed: 73 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -732,6 +732,78 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
732732
dev->user2.val = user2_reg;
733733
}
734734

735+
#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI_MEM_PES_END_INT_ENA_M
736+
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_SPI1_INTR_SOURCE
737+
738+
/**
739+
* @brief Get the address of the interrupt status register.
740+
*
741+
* This function returns a pointer to the interrupt status register of the SPI memory device.
742+
*
743+
* @param[in] dev Pointer to the SPI memory device structure.
744+
* @return volatile void* Pointer to the interrupt status register.
745+
*/
746+
static inline volatile void *spimem_flash_ll_get_interrupt_status_reg(spi_mem_dev_t *dev)
747+
{
748+
return &dev->int_st;
749+
}
750+
751+
/**
752+
* @brief Clear specific interrupt status bits.
753+
*
754+
* This function clears the specified interrupt bits in the interrupt clear register of the SPI memory device.
755+
*
756+
* @param[in] dev Pointer to the SPI memory device structure.
757+
* @param[in] mask Bitmask specifying which interrupt bits to clear.
758+
*/
759+
__attribute__((always_inline))
760+
static inline void spimem_flash_ll_clear_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
761+
{
762+
dev->int_clr.val = mask;
763+
}
764+
765+
/**
766+
* @brief Enable specific interrupt bits.
767+
*
768+
* This function enables the specified interrupts in the interrupt enable register of the SPI memory device.
769+
*
770+
* @param[in] dev Pointer to the SPI memory device structure.
771+
* @param[in] mask Bitmask specifying which interrupt bits to enable.
772+
*/
773+
__attribute__((always_inline))
774+
static inline void spimem_flash_ll_enable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
775+
{
776+
dev->int_ena.val |= mask;
777+
}
778+
779+
/**
780+
* @brief Disable specific interrupt bits.
781+
*
782+
* This function disables the specified interrupts in the interrupt enable register of the SPI memory device.
783+
*
784+
* @param[in] dev Pointer to the SPI memory device structure.
785+
* @param[in] mask Bitmask specifying which interrupt bits to disable.
786+
*/
787+
__attribute__((always_inline))
788+
static inline void spimem_flash_ll_disable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
789+
{
790+
dev->int_ena.val &= (~mask);
791+
}
792+
793+
/**
794+
* @brief Get the current interrupt status.
795+
*
796+
* This function retrieves the current interrupt status from the interrupt status register of the SPI memory device.
797+
*
798+
* @param[in] dev Pointer to the SPI memory device structure.
799+
* @param[out] intr_status Pointer to a variable where the interrupt status will be stored.
800+
*/
801+
__attribute__((always_inline))
802+
static inline void spimem_flash_ll_get_intr_mask(spi_mem_dev_t *dev, uint32_t *intr_status)
803+
{
804+
*intr_status = dev->int_st.val;
805+
}
806+
735807
#ifdef __cplusplus
736808
}
737809
#endif

‎components/hal/esp32c5/include/hal/spimem_flash_ll.h‎

Lines changed: 73 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -763,6 +763,78 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
763763
dev->user2.val = user2_reg;
764764
}
765765

766+
#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI_MEM_PES_END_INT_ENA_M
767+
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_INTR_SOURCE
768+
769+
/**
770+
* @brief Get the address of the interrupt status register.
771+
*
772+
* This function returns a pointer to the interrupt status register of the SPI memory device.
773+
*
774+
* @param[in] dev Pointer to the SPI memory device structure.
775+
* @return volatile void* Pointer to the interrupt status register.
776+
*/
777+
static inline volatile void *spimem_flash_ll_get_interrupt_status_reg(spi_mem_dev_t *dev)
778+
{
779+
return &dev->int_st;
780+
}
781+
782+
/**
783+
* @brief Clear specific interrupt status bits.
784+
*
785+
* This function clears the specified interrupt bits in the interrupt clear register of the SPI memory device.
786+
*
787+
* @param[in] dev Pointer to the SPI memory device structure.
788+
* @param[in] mask Bitmask specifying which interrupt bits to clear.
789+
*/
790+
__attribute__((always_inline))
791+
static inline void spimem_flash_ll_clear_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
792+
{
793+
dev->int_clr.val = mask;
794+
}
795+
796+
/**
797+
* @brief Enable specific interrupt bits.
798+
*
799+
* This function enables the specified interrupts in the interrupt enable register of the SPI memory device.
800+
*
801+
* @param[in] dev Pointer to the SPI memory device structure.
802+
* @param[in] mask Bitmask specifying which interrupt bits to enable.
803+
*/
804+
__attribute__((always_inline))
805+
static inline void spimem_flash_ll_enable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
806+
{
807+
dev->int_ena.val |= mask;
808+
}
809+
810+
/**
811+
* @brief Disable specific interrupt bits.
812+
*
813+
* This function disables the specified interrupts in the interrupt enable register of the SPI memory device.
814+
*
815+
* @param[in] dev Pointer to the SPI memory device structure.
816+
* @param[in] mask Bitmask specifying which interrupt bits to disable.
817+
*/
818+
__attribute__((always_inline))
819+
static inline void spimem_flash_ll_disable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
820+
{
821+
dev->int_ena.val &= (~mask);
822+
}
823+
824+
/**
825+
* @brief Get the current interrupt status.
826+
*
827+
* This function retrieves the current interrupt status from the interrupt status register of the SPI memory device.
828+
*
829+
* @param[in] dev Pointer to the SPI memory device structure.
830+
* @param[out] intr_status Pointer to a variable where the interrupt status will be stored.
831+
*/
832+
__attribute__((always_inline))
833+
static inline void spimem_flash_ll_get_intr_mask(spi_mem_dev_t *dev, uint32_t *intr_status)
834+
{
835+
*intr_status = dev->int_st.val;
836+
}
837+
766838
#ifdef __cplusplus
767839
}
768840
#endif

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