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feat(driver_spi): add h21 spi drivers supports
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‎components/esp_driver_sdspi/test_apps/sdspi/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2-
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
1+
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2+
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

‎components/esp_driver_spi/src/gpspi/spi_master.c‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -115,8 +115,8 @@ We have two bits to control the interrupt:
115115
#include "esp_private/periph_ctrl.h"
116116
#include "esp_private/spi_common_internal.h"
117117
#include "esp_private/spi_master_internal.h"
118+
#include "esp_private/esp_clk_tree_common.h"
118119
#include "driver/spi_master.h"
119-
#include "esp_clk_tree.h"
120120
#include "clk_ctrl_os.h"
121121
#include "esp_log.h"
122122
#include "esp_check.h"
@@ -415,12 +415,10 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa
415415
SPI_CHECK(periph_rtc_dig_clk8m_enable(), "the selected clock not available", ESP_ERR_INVALID_STATE);
416416
}
417417
#endif
418-
spi_clock_source_t clk_src = SPI_CLK_SRC_DEFAULT;
418+
spi_clock_source_t clk_src = dev_config->clock_source ? dev_config->clock_source : SPI_CLK_SRC_DEFAULT;
419419
uint32_t clock_source_hz = 0;
420420
uint32_t clock_source_div = 1;
421-
if (dev_config->clock_source) {
422-
clk_src = dev_config->clock_source;
423-
}
421+
esp_clk_tree_enable_src(clk_src, true);
424422
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz);
425423
#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
426424
SPI_CHECK((dev_config->clock_speed_hz > 0) && (dev_config->clock_speed_hz <= MIN(clock_source_hz / 2, (80 * 1000000))), "invalid sclk speed", ESP_ERR_INVALID_ARG);
@@ -584,7 +582,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
584582
}
585583

586584
#if SOC_SPI_SUPPORT_CLK_RC_FAST
587-
if (handle->cfg.clock_source == SPI_CLK_SRC_RC_FAST) {
585+
if (handle->hal_dev.timing_conf.clock_source == SPI_CLK_SRC_RC_FAST) {
588586
// If no transactions from other device, acquire the bus to switch module clock to `SPI_CLK_SRC_DEFAULT`
589587
// because `SPI_CLK_SRC_RC_FAST` will be disabled then, which block following transactions
590588
if (handle->host->cur_cs == DEV_NUM_MAX) {
@@ -597,6 +595,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
597595
periph_rtc_dig_clk8m_disable();
598596
}
599597
#endif
598+
esp_clk_tree_enable_src(handle->hal_dev.timing_conf.clock_source, false);
600599

601600
//return
602601
int spics_io_num = handle->cfg.spics_io_num;

‎components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h‎

Lines changed: 74 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1,93 +1,109 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#pragma once
88

99
#if CONFIG_IDF_TARGET_ESP32
10-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 16*1000*1000
11-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
12-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
10+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 16*1000*1000
11+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
12+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
1313
#if !CONFIG_FREERTOS_SMP // IDF-5223
14-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 34 // TODO: IDF-5180
15-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 // TODO: IDF-5180
14+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 34 // TODO: IDF-5180
15+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30 // TODO: IDF-5180
1616
#else
17-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 50
18-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 50
17+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 50
18+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 50
1919
#endif
2020

2121
#elif CONFIG_IDF_TARGET_ESP32S2
22-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
23-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
24-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
25-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
26-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
22+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
23+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
24+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
25+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 32
26+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30
2727

2828
#elif CONFIG_IDF_TARGET_ESP32S3
29-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
30-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
31-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
32-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
33-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
29+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
30+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
31+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
32+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 32
33+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30
3434

3535
#elif CONFIG_IDF_TARGET_ESP32C2
36-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
37-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 23
38-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 18
39-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 47
40-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 42
36+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
37+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 23
38+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 18
39+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 47
40+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 42
4141

4242
#elif CONFIG_IDF_TARGET_ESP32C3
43-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
43+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
4444
#if !CONFIG_FREERTOS_SMP // IDF-5223
45-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
46-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
47-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 33
48-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30
45+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
46+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
47+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 33
48+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 30
4949
#else
50-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17
51-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 17
52-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 60
53-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 60
50+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 17
51+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 17
52+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 60
53+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 60
5454
#endif
5555

5656
#elif CONFIG_IDF_TARGET_ESP32C6
57-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26666*1000
58-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 35 //TODO: IDF-9551, check perform
59-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 17
60-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 32
61-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
57+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 26666*1000
58+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 35 //TODO: IDF-9551, check perform
59+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 17
60+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 32
61+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
6262

6363
#elif CONFIG_IDF_TARGET_ESP32H2
64-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 24*1000*1000
65-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 32
66-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 25
67-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 61
68-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 54
64+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 24*1000*1000
65+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 32
66+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 25
67+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 61
68+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 54
6969

7070
#elif CONFIG_IDF_TARGET_ESP32P4
71-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 20*1000*1000
72-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 44
73-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 28
74-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 26
75-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 12
71+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 20*1000*1000
72+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 44
73+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 28
74+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 26
75+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 12
7676

7777
#elif CONFIG_IDF_TARGET_ESP32C5
78-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
79-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 24
80-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
81-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 22
82-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 12
78+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
79+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 24
80+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 15
81+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 22
82+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 12
8383

8484
#elif CONFIG_IDF_TARGET_ESP32C61
85-
#define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 40*1000*1000
86-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32
87-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 19
88-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 29
89-
#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 14
85+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 40*1000*1000
86+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 32
87+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 19
88+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 29
89+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 14
9090

91+
#elif CONFIG_IDF_TARGET_ESP32H21
92+
#if SOC_CLK_TREE_SUPPORTED
93+
//TODO: [ESP32H21] IDF-11521 update perform data according to `TEST_CASE("spi_speed", "[spi]")`
94+
//Also update this value in doc spi_master.rst:535
95+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 32*1000*1000
96+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 0 // need update to real_val + 3
97+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 0 // need update to real_val + 3
98+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 0 // need update to real_val + 3
99+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 0 // need update to real_val + 3
91100
#else
92-
#pragma message "`spi_performance.h` is not updated with your target"
101+
// Remove after SOC_CLK_TREE_SUPPORTED
102+
#define IDF_TARGET_MAX_SPI_CLK_FREQ 32*1000*1000
103+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 1000
104+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 1000
105+
#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 1000
106+
#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 1000
107+
#endif
108+
93109
#endif

‎components/esp_driver_spi/test_apps/master/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2-
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
1+
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2+
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

‎components/esp_driver_spi/test_apps/master/main/test_spi_master.c‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -114,6 +114,8 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
114114
for (int i = 0; i < TEST_CLK_TIMES; i++) {
115115
check_spi_pre_n_for(clk_param_40m[i][0], clk_param_40m[i][1], clk_param_40m[i][2]);
116116
}
117+
} else {
118+
ESP_LOGW(TAG, "Don't find any routing param!!");
117119
}
118120

119121
TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
@@ -147,7 +149,7 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
147149
spi_device_handle_t handle;
148150
spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
149151
devcfg.clock_source = spi_clk_sour[sour_idx];
150-
devcfg.clock_speed_hz = MIN(IDF_PERFORMANCE_MAX_SPI_CLK_FREQ, clock_source_hz) >> test_time;
152+
devcfg.clock_speed_hz = MIN(IDF_TARGET_MAX_SPI_CLK_FREQ, clock_source_hz) >> test_time;
151153
devcfg.flags |= SPI_DEVICE_HALFDUPLEX; //esp32 half duplex to work on high freq
152154
#if SOC_SPI_SUPPORT_CLK_RC_FAST
153155
if (devcfg.clock_source == SPI_CLK_SRC_RC_FAST) {
@@ -170,6 +172,9 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
170172
end = esp_timer_get_time();
171173
int trans_cost = end - start;
172174
int time_tolerance = trans_cost_us_predict * TEST_TRANS_TIME_BIAS_RATIO;
175+
#if !SOC_CLK_TREE_SUPPORTED
176+
time_tolerance *= 2; //cpu is executing too slow before clock supported
177+
#endif
173178
printf("real_freq %dk predict_cost %d real_cost_us %d diff %d tolerance %d us\n", real_freq_khz, trans_cost_us_predict, trans_cost, (trans_cost - trans_cost_us_predict), time_tolerance);
174179

175180
TEST_ASSERT_LESS_THAN_UINT32(time_tolerance, abs(trans_cost - trans_cost_us_predict));
@@ -197,7 +202,7 @@ TEST_CASE("test_device_dynamic_freq_update", "[spi]")
197202
.length = sizeof(master_send) * 8,
198203
};
199204

200-
trans_cfg.override_freq_hz = IDF_PERFORMANCE_MAX_SPI_CLK_FREQ;
205+
trans_cfg.override_freq_hz = IDF_TARGET_MAX_SPI_CLK_FREQ;
201206
for (int i = 1; i < 15; i++) {
202207
TEST_ESP_OK(spi_device_transmit(dev0, &trans_cfg));
203208
spi_device_get_actual_freq(dev0, &master_send);
@@ -1463,7 +1468,7 @@ TEST_CASE("spi_speed", "[spi]")
14631468
}
14641469
#ifndef CONFIG_SPIRAM
14651470
printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_NO_POLLING", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
1466-
TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
1471+
TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_INTR_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
14671472
#endif
14681473

14691474
//acquire the bus to send polling transactions faster
@@ -1481,7 +1486,7 @@ TEST_CASE("spi_speed", "[spi]")
14811486
}
14821487
#ifndef CONFIG_SPIRAM
14831488
printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLLING", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
1484-
TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
1489+
TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_POLL_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
14851490
#endif
14861491

14871492
//release the bus
@@ -1501,7 +1506,7 @@ TEST_CASE("spi_speed", "[spi]")
15011506
}
15021507
#ifndef CONFIG_SPIRAM
15031508
printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_NO_POLLING_NO_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
1504-
TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
1509+
TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_INTR_CPU, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
15051510
#endif
15061511

15071512
//acquire the bus to send polling transactions faster
@@ -1519,7 +1524,7 @@ TEST_CASE("spi_speed", "[spi]")
15191524
}
15201525
#ifndef CONFIG_SPIRAM
15211526
printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLLING_NO_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
1522-
TEST_ASSERT_LESS_THAN_INT(IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
1527+
TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_POLL_CPU, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
15231528
#endif
15241529

15251530
//release the bus
@@ -1830,6 +1835,7 @@ TEST_CASE("test_bus_free_safty_to_remain_devices", "[spi]")
18301835
TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
18311836
}
18321837

1838+
#if SOC_LIGHT_SLEEP_SUPPORTED
18331839
TEST_CASE("test_spi_master_sleep_retention", "[spi]")
18341840
{
18351841
// Prepare a TOP PD sleep
@@ -1959,3 +1965,4 @@ TEST_CASE("test_spi_master_auto_sleep_retention", "[spi]")
19591965
TEST_ESP_OK(esp_pm_configure(&pm_config));
19601966
}
19611967
#endif //CONFIG_PM_ENABLE
1968+
#endif //SOC_LIGHT_SLEEP_SUPPORTED

‎components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -292,6 +292,7 @@ TEST_CASE("spi_master: test_sct_dma_desc_oob_on_tail", "[spi]")
292292
TEST_ESP_OK(spi_bus_free(SPI2_HOST));
293293
}
294294

295+
#if SOC_LIGHT_SLEEP_SUPPORTED
295296
/*-----------------------------------------------------------
296297
* Sleep Retention Test
297298
*-----------------------------------------------------------*/
@@ -416,3 +417,4 @@ static void sleep_slave(void)
416417
TEST_ESP_OK(spi_slave_hd_deinit(SPI2_HOST));
417418
}
418419
TEST_CASE_MULTIPLE_DEVICES("test_spi_master_sct_sleep_retention", "[spi_ms]", sleep_master, sleep_slave);
420+
#endif //SOC_LIGHT_SLEEP_SUPPORTED

‎components/esp_driver_spi/test_apps/param/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2-
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
1+
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2+
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

‎components/esp_driver_spi/test_apps/param/main/test_spi_param.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -1269,12 +1269,12 @@ TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "")
12691269
#define TEST_STEP_LEN 96
12701270
#define TEST_STEP 2
12711271
static int s_spi_bus_freq[] = {
1272-
IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 10,
1273-
IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 7,
1274-
IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 4,
1275-
IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 2,
1272+
IDF_TARGET_MAX_SPI_CLK_FREQ / 10,
1273+
IDF_TARGET_MAX_SPI_CLK_FREQ / 7,
1274+
IDF_TARGET_MAX_SPI_CLK_FREQ / 4,
1275+
IDF_TARGET_MAX_SPI_CLK_FREQ / 2,
12761276
#if !CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-8313, update P4 defaulte clock source
1277-
IDF_PERFORMANCE_MAX_SPI_CLK_FREQ,
1277+
IDF_TARGET_MAX_SPI_CLK_FREQ,
12781278
#endif
12791279
};
12801280

‎components/esp_driver_spi/test_apps/slave/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
1-
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2-
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
1+
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
2+
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

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