Skip to content

Commit 51a7f45

Browse files
L-KAYAL-KAYA
committed
Merge branch 'ci/re_enable_i2s_pytest_exceptions' into 'master'
ci(i2s): re-enable example pytest exceptions Closes IDF-10007 See merge request espressif/esp-idf!36271
2 parents 4393a0d + 364371a commit 51a7f45

File tree

3 files changed

+50
-54
lines changed

3 files changed

+50
-54
lines changed

‎examples/peripherals/i2s/i2s_basic/i2s_pdm/pytest_i2s_pdm.py‎

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
1+
# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
22
# SPDX-License-Identifier: CC0-1.0
33
import pytest
44
from pytest_embedded import Dut
@@ -21,14 +21,13 @@
2121
def test_i2s_pdm_tx_example(dut: Dut) -> None:
2222
dut.expect(r'I2S PDM TX example start', timeout=5)
2323
dut.expect(r'---------------------------', timeout=5)
24-
# TODO: IDF-10007, reopen
25-
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
26-
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
27-
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
28-
# dut.expect(r'D \(([0-9]+)\) i2s_pdm: Clock division info: \[sclk\] ([0-9]+) Hz '
29-
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
30-
# dut.expect(r'D \(([0-9]+)\) i2s_pdm: The tx channel on I2S0 has been initialized to PDM TX mode successfully', timeout=5)
31-
# dut.expect(r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled', timeout=5)
24+
dut.expect(r'i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
25+
dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
26+
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
27+
dut.expect(r'i2s_pdm: Clock division info: \[sclk\] ([0-9]+) Hz '
28+
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
29+
dut.expect(r'i2s_pdm: The tx channel on I2S0 has been initialized to PDM TX mode successfully', timeout=5)
30+
dut.expect(r'i2s_common: i2s tx channel enabled', timeout=5)
3231
dut.expect(r'Playing bass `twinkle twinkle little star`', timeout=5)
3332

3433

@@ -44,11 +43,10 @@ def test_i2s_pdm_tx_example(dut: Dut) -> None:
4443
def test_i2s_pdm_rx_example(dut: Dut) -> None:
4544
dut.expect(r'I2S PDM RX example start', timeout=5)
4645
dut.expect(r'---------------------------', timeout=5)
47-
# TODO: IDF-10007, reopen
48-
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
49-
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
50-
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
51-
# dut.expect(r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled', timeout=5)
46+
dut.expect(r'i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
47+
dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
48+
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
49+
dut.expect(r'i2s_common: i2s rx channel enabled', timeout=5)
5250
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
5351
dut.expect(r'-----------------------------------', timeout=5)
5452
dut.expect(r'\[0\] ([-]?[0-9]+) \[1\] ([-]?[0-9]+) \[2\] ([-]?[0-9]+) \[3\] ([-]?[0-9]+)', timeout=5)

‎examples/peripherals/i2s/i2s_basic/i2s_std/pytest_i2s_std.py‎

Lines changed: 19 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
1+
# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
22
# SPDX-License-Identifier: CC0-1.0
33
import pytest
44
from pytest_embedded import Dut
@@ -16,25 +16,24 @@
1616
@pytest.mark.generic
1717
def test_i2s_basic_example(dut: Dut) -> None:
1818

19-
# TODO: IDF-10007, reopen
20-
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
21-
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
22-
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
23-
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
24-
# dut.expect(r'D \(([0-9]+)\) i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
25-
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
26-
# dut.expect(r'D \(([0-9]+)\) i2s_std: The tx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
27-
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
28-
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
29-
# dut.expect(r'D \(([0-9]+)\) i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
30-
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
31-
# dut.expect(r'D \(([0-9]+)\) i2s_std: The rx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
32-
# chan_enable_pattern = [
33-
# r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled',
34-
# r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled'
35-
# ]
36-
# dut.expect(chan_enable_pattern, timeout=5)
37-
# dut.expect(chan_enable_pattern, timeout=5)
19+
dut.expect(r'i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
20+
dut.expect(r'i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
21+
dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
22+
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
23+
dut.expect(r'i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
24+
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
25+
dut.expect(r'i2s_std: The tx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
26+
dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
27+
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
28+
dut.expect(r'i2s_std: Clock division info: \[sclk\] ([0-9]+) Hz '
29+
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
30+
dut.expect(r'i2s_std: The rx channel on I2S0 has been initialized to STD mode successfully', timeout=5)
31+
chan_enable_pattern = [
32+
r'i2s_common: i2s tx channel enabled',
33+
r'i2s_common: i2s rx channel enabled'
34+
]
35+
dut.expect(chan_enable_pattern, timeout=5)
36+
dut.expect(chan_enable_pattern, timeout=5)
3837
dut.expect(r'Write Task: i2s write ([0-9]+) bytes', timeout=5)
3938
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
4039
dut.expect(r'-----------------------------------', timeout=5)

‎examples/peripherals/i2s/i2s_basic/i2s_tdm/pytest_i2s_tdm.py‎

Lines changed: 19 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
1+
# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
22
# SPDX-License-Identifier: CC0-1.0
33
import pytest
44
from pytest_embedded import Dut
@@ -14,25 +14,24 @@
1414
@pytest.mark.generic
1515
def test_i2s_tdm_example(dut: Dut) -> None:
1616

17-
# TODO: IDF-10007, reopen
18-
# dut.expect(r'D \(([0-9]+)\) i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
19-
# dut.expect(r'D \(([0-9]+)\) i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
20-
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
21-
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
22-
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
23-
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
24-
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: The tx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
25-
# dut.expect(r'D \(([0-9]+)\) i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
26-
# r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
27-
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
28-
# r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
29-
# dut.expect(r'D \(([0-9]+)\) i2s_tdm: The rx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
30-
# chan_enable_pattern = [
31-
# r'D \(([0-9]+)\) i2s_common: i2s tx channel enabled',
32-
# r'D \(([0-9]+)\) i2s_common: i2s rx channel enabled'
33-
# ]
34-
# dut.expect(chan_enable_pattern, timeout=5)
35-
# dut.expect(chan_enable_pattern, timeout=5)
17+
dut.expect(r'i2s_common: tx channel is registered on I2S0 successfully', timeout=5)
18+
dut.expect(r'i2s_common: rx channel is registered on I2S0 successfully', timeout=5)
19+
dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
20+
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
21+
dut.expect(r'i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
22+
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
23+
dut.expect(r'i2s_tdm: The tx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
24+
dut.expect(r'i2s_common: DMA malloc info: dma_desc_num = ([0-9]+), '
25+
r'dma_desc_buf_size = dma_frame_num \* slot_num \* data_bit_width = ([0-9]+)', timeout=5)
26+
dut.expect(r'i2s_tdm: Clock division info: \[sclk\] ([0-9]+) Hz '
27+
r'\[mdiv\] ([0-9]+) \[mclk\] ([0-9]+) Hz \[bdiv\] ([0-9]+) \[bclk\] ([0-9]+) Hz', timeout=5)
28+
dut.expect(r'i2s_tdm: The rx channel on I2S0 has been initialized to TDM mode successfully', timeout=5)
29+
chan_enable_pattern = [
30+
r'i2s_common: i2s tx channel enabled',
31+
r'i2s_common: i2s rx channel enabled'
32+
]
33+
dut.expect(chan_enable_pattern, timeout=5)
34+
dut.expect(chan_enable_pattern, timeout=5)
3635
dut.expect(r'Write Task: i2s write ([0-9]+) bytes', timeout=5)
3736
dut.expect(r'Read Task: i2s read ([0-9]+) bytes', timeout=5)
3837
dut.expect(r'-----------------------------------', timeout=5)

0 commit comments

Comments
 (0)