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songruosongruo
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Merge branch 'bugfix/periph_clk_init_p4' into 'master'
fix(esp_system): hp periph clk should not be gated on core/system reset Closes FCS-1638 See merge request espressif/esp-idf!35317
2 parents bcd80c9 + 7b852fa commit 547fa88

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3 files changed

+37
-26
lines changed

3 files changed

+37
-26
lines changed

‎components/bootloader_support/src/bootloader_console.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,12 @@ void bootloader_console_init(void)
7474
// Enable the peripheral
7575
uart_ll_enable_bus_clock(uart_num, true);
7676
uart_ll_reset_register(uart_num);
77+
// Set clock source
78+
#if SOC_UART_SUPPORT_XTAL_CLK
79+
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), (soc_module_clk_t)UART_SCLK_XTAL);
80+
#else
81+
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), (soc_module_clk_t)UART_SCLK_APB);
82+
#endif
7783
// Reset TX and RX FIFOs
7884
uart_ll_txfifo_rst(UART_LL_GET_HW(uart_num));
7985
uart_ll_rxfifo_rst(UART_LL_GET_HW(uart_num));

‎components/esp_system/port/soc/esp32c6/clk.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -316,8 +316,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
316316
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \
317317
|| (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
318318
_lp_i2c_ll_enable_bus_clock(0, false);
319-
_lp_uart_ll_enable_bus_clock(0, false);
320319
lp_uart_ll_sclk_disable(0);
320+
_lp_uart_ll_enable_bus_clock(0, false);
321321
lp_core_ll_enable_bus_clock(false);
322322
_lp_clkrst_ll_enable_rng_clock(false);
323323

‎components/esp_system/port/soc/esp32p4/clk.c‎

Lines changed: 30 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -244,9 +244,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
244244
}
245245

246246
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
247-
if ((rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU_MWDT) \
248-
&& (rst_reason != RESET_REASON_CPU_RWDT) && (rst_reason != RESET_REASON_CPU_JTAG) \
249-
&& (rst_reason != RESET_REASON_CPU_LOCKUP)) {
247+
// HP related clock control
248+
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN)) {
249+
// hp_sys_clkrst register gets reset only if chip reset or pmu powers down hp
250250
_gdma_ll_enable_bus_clock(0, false);
251251
_gdma_ll_enable_bus_clock(1, false);
252252
_pau_ll_enable_bus_clock(false);
@@ -357,33 +357,38 @@ __attribute__((weak)) void esp_perip_clk_init(void)
357357
#endif
358358
}
359359

360+
// LP related clock control
360361
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \
361362
|| (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_BROWN_OUT)) {
362-
_lp_uart_ll_enable_bus_clock(0, false);
363+
// lpperi,lp peripheral registers get reset for reset level equal or higher than system reset
363364
lp_uart_ll_sclk_disable(0);
365+
_lp_uart_ll_enable_bus_clock(0, false);
364366
_rtcio_ll_enable_io_clock(false);
365-
// LP_Peri & Clock Control
366-
_uart_ll_enable_pad_sleep_clock(&UART0, false);
367-
_uart_ll_enable_pad_sleep_clock(&UART1, false);
368-
_uart_ll_enable_pad_sleep_clock(&UART2, false);
369-
_uart_ll_enable_pad_sleep_clock(&UART3, false);
370-
_uart_ll_enable_pad_sleep_clock(&UART4, false);
371-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN);
372-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN);
373-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S2_MCLK_EN);
374-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S1_MCLK_EN);
375-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S0_MCLK_EN);
376-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN);
377-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN);
378-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN);
379-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PLL_8M_CLK_EN);
380-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_AUDIO_PLL_CLK_EN);
381-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL2_CLK_EN);
382-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL1_CLK_EN);
383-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL0_CLK_EN);
367+
368+
if (rst_reason == RESET_REASON_CHIP_POWER_ON) {
369+
// lp_aon_clkrst, lp_system registers get reset only if chip reset
370+
_uart_ll_enable_pad_sleep_clock(&UART0, false);
371+
_uart_ll_enable_pad_sleep_clock(&UART1, false);
372+
_uart_ll_enable_pad_sleep_clock(&UART2, false);
373+
_uart_ll_enable_pad_sleep_clock(&UART3, false);
374+
_uart_ll_enable_pad_sleep_clock(&UART4, false);
375+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN);
376+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN);
377+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S2_MCLK_EN);
378+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S1_MCLK_EN);
379+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S0_MCLK_EN);
380+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN);
381+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN);
382+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN);
383+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PLL_8M_CLK_EN);
384+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_AUDIO_PLL_CLK_EN);
385+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL2_CLK_EN);
386+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL1_CLK_EN);
387+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL0_CLK_EN);
384388
#if !CONFIG_SPIRAM_BOOT_INIT
385-
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_MPLL_500M_CLK_EN);
389+
REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_MPLL_500M_CLK_EN);
386390
#endif
387-
REG_CLR_BIT(LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG, LP_SYSTEM_REG_CPU_CLK_EN);
391+
REG_CLR_BIT(LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG, LP_SYSTEM_REG_CPU_CLK_EN);
392+
}
388393
}
389394
}

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