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Jiang Jiang Jian
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Merge branch 'chip/add_wifi_support_for_esp32c61_eco3_rebase_master' into 'master'
feat(wifi): add esp32c61 eco3 wifi support Closes IDF-9244, IDF-9245, IDF-9246, IDF-9247, IDF-9248, IDF-9250, IDF-9513, IDF-10382, IDF-10384, IDF-11003, IDF-11004, IDF-10643, IDF-10642, IDF-10619, IDF-10634, IDF-10632, IDF-10636, IDF-10637, IDF-10626, IDF-10620, IDF-10621, IDF-10623, IDF-10635, IDF-10629, IDF-10622, IDF-10624, and IDF-10625 See merge request espressif/esp-idf!39720
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‎components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -18,24 +18,24 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
1818
{
1919
const static sleep_retention_entries_config_t pcr_regs_retention[] = {
2020
/* Enable i2c master clock */
21-
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) },
21+
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) },
2222
/* Start BBPLL self-calibration */
23-
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
24-
[2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
23+
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
24+
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
2525
/* Wait calibration done */
26-
[3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) },
26+
[3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) },
2727
/* Stop BBPLL self-calibration */
28-
[4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
29-
[5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
28+
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) },
29+
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) },
3030
/* Clock configuration retention */
31-
[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), PMU_CLK_STATE0_REG, PMU_STABLE_XPD_BBPLL_STATE, PMU_STABLE_XPD_BBPLL_STATE_M, 1, 0), .owner = ENTRY(0)}, /* Wait PMU_WAIT_XTL_STABLE done */
32-
[7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
33-
[8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
31+
[6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), PMU_CLK_STATE0_REG, PMU_STABLE_XPD_BBPLL_STATE, PMU_STABLE_XPD_BBPLL_STATE_M, 1, 0), .owner = ENTRY(0) }, /* Wait PMU_WAIT_XTL_STABLE done */
32+
[7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(7), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
33+
[8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
34+
[9] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(9), LP_ANA_POWER_GLITCH_CNTL_REG, 0, LP_ANA_POWER_GLITCH_RESET_ENA_M,0, 1), .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */
35+
[10] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF, LP_ANA_POWER_GLITCH_RESET_ENA_M,1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */
3436
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
35-
[9] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(9), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
37+
[11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
3638
#endif
37-
[10] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0, LP_ANA_POWER_GLITCH_RESET_ENA_M, 0, 1), .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */
38-
[11] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(11), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF, LP_ANA_POWER_GLITCH_RESET_ENA_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */
3939
};
4040

4141
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);

‎components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c‎

Lines changed: 0 additions & 152 deletions
This file was deleted.

‎components/esp_hw_support/port/esp32c61/pmu_param.c‎

Lines changed: 50 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -202,66 +202,69 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
202202
}
203203

204204
#define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
205-
.bias = { \
206-
.xpd_bias = 1, \
207-
.dbg_atten = 0x0, \
208-
.pd_cur = 0, \
209-
.bias_sleep = 0 \
205+
.bias = { \
206+
.xpd_bias = 1, \
207+
.dbg_atten = 0x0, \
208+
.pd_cur = 0, \
209+
.bias_sleep = 0 \
210210
}, \
211-
.regulator0 = { \
212-
.lp_dbias_vol = 0xd, \
213-
.hp_dbias_vol = 0x1c,\
214-
.dbias_sel = 1, \
215-
.dbias_init = 1, \
216-
.slp_mem_xpd = 0, \
217-
.slp_logic_xpd = 0, \
218-
.xpd = 1, \
219-
.slp_mem_dbias = 0, \
220-
.slp_logic_dbias = 0, \
221-
.dbias = HP_CALI_DBIAS_DEFAULT \
211+
.regulator0 = { \
212+
.slp_connect_en_active = 1, \
213+
.lp_dbias_vol = 0xd, \
214+
.hp_dbias_vol = 0x1c,\
215+
.dbias_sel = 1, \
216+
.dbias_init_active = 1, \
217+
.slp_mem_xpd = 0, \
218+
.slp_logic_xpd = 0, \
219+
.xpd = 1, \
220+
.slp_mem_dbias = 0, \
221+
.slp_logic_dbias = 0, \
222+
.dbias = HP_CALI_DBIAS_DEFAULT \
222223
}, \
223-
.regulator1 = { \
224-
.drv_b = 0x0 \
224+
.regulator1 = { \
225+
.drv_b = 0x0 \
225226
} \
226227
}
227228

228229
#define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \
229-
.bias = { \
230-
.xpd_bias = 0, \
231-
.dbg_atten = 0x0, \
232-
.pd_cur = 0, \
233-
.bias_sleep = 0 \
230+
.bias = { \
231+
.xpd_bias = 0, \
232+
.dbg_atten = 0x0,\
233+
.pd_cur = 0, \
234+
.bias_sleep = 0 \
234235
}, \
235-
.regulator0 = { \
236-
.slp_mem_xpd = 0, \
237-
.slp_logic_xpd = 0, \
238-
.xpd = 1, \
239-
.slp_mem_dbias = 0, \
240-
.slp_logic_dbias = 0, \
241-
.dbias = HP_CALI_DBIAS_DEFAULT \
236+
.regulator0 = { \
237+
.slp_connect_en_modem = 1, \
238+
.slp_mem_xpd = 0, \
239+
.slp_logic_xpd = 0, \
240+
.xpd = 1, \
241+
.slp_mem_dbias = 0, \
242+
.slp_logic_dbias = 0, \
243+
.dbias = HP_CALI_DBIAS_DEFAULT \
242244
}, \
243-
.regulator1 = { \
244-
.drv_b = 0x0 \
245+
.regulator1 = { \
246+
.drv_b = 0x0 \
245247
} \
246248
}
247249

248250
#define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
249-
.bias = { \
250-
.xpd_bias = 0, \
251-
.dbg_atten = 0x0, \
252-
.pd_cur = 0, \
253-
.bias_sleep = 0 \
251+
.bias = { \
252+
.xpd_bias = 0, \
253+
.dbg_atten = 0x0,\
254+
.pd_cur = 0, \
255+
.bias_sleep = 0 \
254256
}, \
255-
.regulator0 = { \
256-
.slp_mem_xpd = 0, \
257-
.slp_logic_xpd = 0, \
258-
.xpd = 1, \
259-
.slp_mem_dbias = 0, \
260-
.slp_logic_dbias = 0, \
261-
.dbias = 1 \
257+
.regulator0 = { \
258+
.slp_connect_en_sleep = 1, \
259+
.slp_mem_xpd = 0, \
260+
.slp_logic_xpd = 0, \
261+
.xpd = 1, \
262+
.slp_mem_dbias = 0, \
263+
.slp_logic_dbias = 0, \
264+
.dbias = 1 \
262265
}, \
263-
.regulator1 = { \
264-
.drv_b = 0x0 \
266+
.regulator1 = { \
267+
.drv_b = 0x0 \
265268
} \
266269
}
267270

‎components/esp_hw_support/sleep_modes.c‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -186,8 +186,8 @@
186186
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
187187
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
188188
#elif CONFIG_IDF_TARGET_ESP32C61
189-
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
190-
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (107)
189+
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (65)
190+
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (70)
191191
#elif CONFIG_IDF_TARGET_ESP32H2
192192
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)
193193
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
@@ -224,12 +224,8 @@
224224
#endif
225225

226226
#if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
227-
#if CONFIG_IDF_TARGET_ESP32C61
228-
#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1232)
229-
#elif CONFIG_IDF_TARGET_ESP32C5
230227
#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1220)
231228
#endif
232-
#endif
233229

234230
#define RTC_MODULE_SLEEP_PREPARE_CYCLES (6)
235231

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