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| 1 | +/* |
| 2 | + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +/* |
| 8 | + * WARNING: |
| 9 | + * |
| 10 | + * This file is shared between the HP and LP cores. |
| 11 | + * Updates to this file should be made carefully and should not include FreeRTOS APIs or other IDF-specific functionalities, such as the interrupt allocator. |
| 12 | + */ |
| 13 | + |
| 14 | +#include "driver/uart_wakeup.h" |
| 15 | +#include "hal/uart_hal.h" |
| 16 | + |
| 17 | +#if SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE |
| 18 | +static esp_err_t uart_char_seq_wk_configure(uart_dev_t *hw, const char* phrase) |
| 19 | +{ |
| 20 | + if (phrase == NULL || phrase[0] == '\0') { |
| 21 | + return ESP_ERR_INVALID_ARG; |
| 22 | + } |
| 23 | + esp_err_t ret = ESP_OK; |
| 24 | + |
| 25 | + uint32_t mask = 0; |
| 26 | + uint32_t index = 0; |
| 27 | + |
| 28 | + while (index < SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN && phrase[index] != '\0') { |
| 29 | + if (phrase[index] == '*') { |
| 30 | + mask |= 1 << index; |
| 31 | + } else { |
| 32 | + uart_ll_set_char_seq_wk_char(hw, index, phrase[index]); |
| 33 | + } |
| 34 | + index++; |
| 35 | + } |
| 36 | + |
| 37 | + if ( |
| 38 | + index == 0 || |
| 39 | + phrase[index - 1] == '*' || |
| 40 | + mask > 0xF |
| 41 | + ) { |
| 42 | + return ESP_ERR_INVALID_ARG; |
| 43 | + } |
| 44 | + uart_ll_set_wakeup_char_seq_mask(hw, mask); |
| 45 | + uart_ll_set_wakeup_char_seq_char_num(hw, index - 1); |
| 46 | + |
| 47 | + return ret; |
| 48 | +} |
| 49 | +#endif |
| 50 | + |
| 51 | +esp_err_t uart_wakeup_setup(uart_port_t uart_num, const uart_wakeup_cfg_t *cfg) |
| 52 | +{ |
| 53 | + |
| 54 | + if (cfg == NULL) { |
| 55 | + return ESP_ERR_INVALID_ARG; |
| 56 | + } |
| 57 | + uart_dev_t *hw = UART_LL_GET_HW(uart_num); |
| 58 | + |
| 59 | + // This should be mocked at ll level if the selection of the UART wakeup mode is not supported by this SOC. |
| 60 | + uart_ll_set_wakeup_mode(hw, cfg->wakeup_mode); |
| 61 | + |
| 62 | + switch (cfg->wakeup_mode) { |
| 63 | +#if SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE |
| 64 | + case UART_WK_MODE_ACTIVE_THRESH: |
| 65 | + // UART_ACTIVE_THRESHOLD register has only 10 bits, and the min value is 3. |
| 66 | + if (cfg->rx_edge_threshold < UART_LL_WAKEUP_EDGE_THRED_MIN || cfg->rx_edge_threshold > UART_LL_WAKEUP_EDGE_THRED_MAX(hw)) { |
| 67 | + return ESP_ERR_INVALID_ARG; |
| 68 | + } |
| 69 | + uart_ll_set_wakeup_edge_thrd(hw, cfg->rx_edge_threshold); |
| 70 | + return ESP_OK; |
| 71 | +#endif |
| 72 | +#if SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE |
| 73 | + case UART_WK_MODE_FIFO_THRESH: |
| 74 | + if (cfg->rx_fifo_threshold > UART_LL_WAKEUP_FIFO_THRED_MAX(hw)) { |
| 75 | + return ESP_ERR_INVALID_ARG; |
| 76 | + } |
| 77 | + uart_ll_set_wakeup_fifo_thrd(hw, cfg->rx_fifo_threshold); |
| 78 | + return ESP_OK; |
| 79 | +#endif |
| 80 | +#if SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE |
| 81 | + case UART_WK_MODE_START_BIT: |
| 82 | + return ESP_OK; |
| 83 | +#endif |
| 84 | +#if SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE |
| 85 | + case UART_WK_MODE_CHAR_SEQ: |
| 86 | + return uart_char_seq_wk_configure(hw, cfg->wake_chars_seq); |
| 87 | +#endif |
| 88 | + } |
| 89 | + |
| 90 | + return ESP_ERR_INVALID_ARG; |
| 91 | +} |
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