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nileshkale123nileshkale123
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feat: enable ecc support for esp32h21
This commmit enabled support for ECC peripheral in ESP32H21.
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3 files changed

+272
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‎components/hal/esp32h21/include/hal/ecc_ll.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,255 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <string.h>
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#include "hal/assert.h"
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#include "hal/ecc_types.h"
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#include "soc/ecc_mult_reg.h"
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#include "soc/pcr_struct.h"
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#include "soc/pcr_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ECC_PARAM_PX = 0x0,
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ECC_PARAM_PY,
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ECC_PARAM_K,
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ECC_PARAM_QX,
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ECC_PARAM_QY,
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ECC_PARAM_QZ,
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} ecc_ll_param_t;
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/**
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* @brief Enable the bus clock for ECC peripheral module
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*
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* @param true to enable the module, false to disable the module
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*/
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static inline void ecc_ll_enable_bus_clock(bool enable)
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{
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PCR.ecc_conf.ecc_clk_en = enable;
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}
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/**
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* @brief Reset the ECC peripheral module
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*/
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static inline void ecc_ll_reset_register(void)
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{
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PCR.ecc_conf.ecc_rst_en = 1;
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PCR.ecc_conf.ecc_rst_en = 0;
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// Clear reset on ECDSA, otherwise ECC is held in reset
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PCR.ecdsa_conf.ecdsa_rst_en = 0;
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}
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static inline void ecc_ll_power_up(void)
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{
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REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
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REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PD);
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}
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static inline void ecc_ll_power_down(void)
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{
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REG_CLR_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_FORCE_PU);
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REG_SET_BIT(PCR_ECC_PD_CTRL_REG, PCR_ECC_MEM_PD);
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}
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static inline void ecc_ll_enable_interrupt(void)
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{
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REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);
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}
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static inline void ecc_ll_disable_interrupt(void)
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{
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REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0);
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}
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static inline void ecc_ll_clear_interrupt(void)
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{
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REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1);
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}
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static inline void ecc_ll_set_mode(ecc_mode_t mode)
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{
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switch(mode) {
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case ECC_MODE_POINT_MUL:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
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break;
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case ECC_MODE_VERIFY:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
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break;
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case ECC_MODE_VERIFY_THEN_POINT_MUL:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
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break;
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case ECC_MODE_JACOBIAN_POINT_MUL:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
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break;
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case ECC_MODE_POINT_ADD:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
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break;
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case ECC_MODE_JACOBIAN_POINT_VERIFY:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
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break;
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case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
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break;
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case ECC_MODE_MOD_ADD:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
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break;
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case ECC_MODE_MOD_SUB:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
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break;
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case ECC_MODE_MOD_MUL:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
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break;
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case ECC_MODE_INVERSE_MUL:
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REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
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break;
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default:
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HAL_ASSERT(false && "Unsupported mode");
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break;
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}
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}
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static inline void ecc_ll_set_curve(ecc_curve_t curve)
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{
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switch(curve) {
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case ECC_CURVE_SECP256R1:
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REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
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break;
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case ECC_CURVE_SECP192R1:
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REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
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break;
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default:
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HAL_ASSERT(false && "Unsupported curve");
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return;
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}
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}
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static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
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{
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switch(base) {
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case ECC_MOD_N:
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REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
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break;
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case ECC_MOD_P:
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REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
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break;
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default:
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HAL_ASSERT(false && "Unsupported curve");
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return;
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}
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}
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static inline void ecc_ll_enable_constant_time_point_mul(bool enable)
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{
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if (enable) {
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REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_SECURITY_MODE);
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} else {
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REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_SECURITY_MODE);
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}
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}
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static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len)
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{
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uint32_t reg;
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uint32_t word;
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switch (param) {
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case ECC_PARAM_PX:
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reg = ECC_MULT_PX_MEM;
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break;
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case ECC_PARAM_PY:
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reg = ECC_MULT_PY_MEM;
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break;
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case ECC_PARAM_K:
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reg = ECC_MULT_K_MEM;
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break;
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case ECC_PARAM_QX:
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reg = ECC_MULT_QX_MEM;
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break;
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case ECC_PARAM_QY:
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reg = ECC_MULT_QY_MEM;
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break;
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case ECC_PARAM_QZ:
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reg = ECC_MULT_QZ_MEM;
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break;
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default:
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HAL_ASSERT(false && "Invalid parameter");
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return;
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}
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for (int i = 0; i < len; i += 4) {
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memcpy(&word, buf + i, 4);
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REG_WRITE(reg + i, word);
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}
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}
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static inline void ecc_ll_start_calc(void)
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{
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REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START);
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}
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static inline int ecc_ll_is_calc_finished(void)
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{
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return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW);
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}
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static inline ecc_mode_t ecc_ll_get_mode(void)
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{
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return (ecc_mode_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE));
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}
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static inline int ecc_ll_get_verification_result(void)
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{
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return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT);
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}
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static inline ecc_curve_t ecc_ll_get_curve(void)
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{
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return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
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}
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static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
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{
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return (ecc_mod_base_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE));
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}
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static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)
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{
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uint32_t reg;
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switch (param) {
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case ECC_PARAM_PX:
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reg = ECC_MULT_PX_MEM;
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break;
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case ECC_PARAM_PY:
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reg = ECC_MULT_PY_MEM;
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break;
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case ECC_PARAM_K:
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reg = ECC_MULT_K_MEM;
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break;
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case ECC_PARAM_QX:
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reg = ECC_MULT_QX_MEM;
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break;
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case ECC_PARAM_QY:
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reg = ECC_MULT_QY_MEM;
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break;
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case ECC_PARAM_QZ:
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reg = ECC_MULT_QZ_MEM;
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break;
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default:
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HAL_ASSERT(false && "Invalid parameter");
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return;
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}
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memcpy(buf, (void *)reg, len);
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}
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#ifdef __cplusplus
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}
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#endif

‎components/soc/esp32h21/include/soc/Kconfig.soc_caps.in‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,14 @@ config SOC_SYSTIMER_SUPPORTED
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bool
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default y
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config SOC_ECC_SUPPORTED
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bool
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default y
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config SOC_ECC_EXTENDED_MODES_SUPPORTED
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bool
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default y
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config SOC_FLASH_ENC_SUPPORTED
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bool
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default y
@@ -299,6 +307,10 @@ config SOC_SHA_SUPPORT_SHA256
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bool
300308
default y
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config SOC_ECC_CONSTANT_TIME_POINT_MUL
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bool
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default y
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config SOC_SPI_PERIPH_NUM
303315
int
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default 2

‎components/soc/esp32h21/include/soc/soc_caps.h‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,8 +47,8 @@
4747
// #define SOC_SHA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11501
4848
// #define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11495
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// #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32H21] IDF-11497
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// #define SOC_ECC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11502
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// #define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11502
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#define SOC_ECC_SUPPORTED 1
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#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
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// #define SOC_ECDSA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11496
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#define SOC_FLASH_ENC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11499
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// #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11500
@@ -373,6 +373,9 @@
373373
#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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376+
/*--------------------------- ECC CAPS ---------------------------------------*/
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#define SOC_ECC_CONSTANT_TIME_POINT_MUL 1
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376379
/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 6

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