fix(system): fixed ram loadable app on p4

Icarus113 · Icarus113 · commit 6933ba39bc78 · 2024-09-09T10:31:48.000+08:00
diff --git a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 #include <stdint.h>
 #include <esp_err.h>
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -27,6 +28,13 @@ esp_err_t bootloader_init_spi_flash(void);
 void bootloader_flash_hardware_init(void);
 #endif
 
+#if SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
+/**
+ * @brief Initialise flash core clock
+ */
+void bootloader_flash_init_core_clock(void);
+#endif  //SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
@@ -19,10 +19,12 @@
 #include "bootloader_init.h"
 #include "hal/mmu_hal.h"
 #include "hal/mmu_ll.h"
+#include "hal/spimem_flash_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
+#include "esp_private/bootloader_flash_internal.h"
 
-void IRAM_ATTR bootloader_flash_update_id()
+void IRAM_ATTR bootloader_flash_update_id(void)
 {
     esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
     chip->device_id = bootloader_read_flash_id();
@@ -33,15 +35,23 @@ void bootloader_flash_update_size(uint32_t size)
     rom_spiflash_legacy_data->chip.chip_size = size;
 }
 
-void IRAM_ATTR bootloader_flash_cs_timing_config()
+void IRAM_ATTR bootloader_flash_cs_timing_config(void)
 {
     SET_PERI_REG_MASK(SPI_MEM_C_USER_REG, SPI_MEM_C_CS_HOLD_M | SPI_MEM_C_CS_SETUP_M);
     SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_HOLD_TIME_V, 0, SPI_MEM_C_CS_HOLD_TIME_S);
     SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S);
 }
 
+void IRAM_ATTR bootloader_flash_init_core_clock(void)
+{
+    _spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
+    _spimem_ctrlr_ll_set_core_clock(0, 6);
+}
+
 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
 {
+    bootloader_flash_init_core_clock();
+
     uint32_t spi_clk_div = 0;
     switch (pfhdr->spi_speed) {
     case ESP_IMAGE_SPI_SPEED_DIV_1:
diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
@@ -109,12 +109,12 @@ static inline void bootloader_hardware_init(void)
     REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10);
     REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
 
+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
     // IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used.
-    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
     if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) {
-        spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
-        spimem_ctrlr_ll_set_core_clock(0, 6);
+        bootloader_flash_init_core_clock();
     }
+#endif
 }
 
 static inline void bootloader_ana_reset_config(void)
diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h
@@ -734,7 +734,7 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou
  * @param clk_src      clock source, see valid sources in type `soc_periph_flash_clk_src_t`
  */
 __attribute__((always_inline))
-static inline void spimem_flash_ll_select_clk_source(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
+static inline void _spimem_flash_ll_select_clk_source(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
 {
     (void)mspi_id;
     uint32_t clk_val = 0;
@@ -759,7 +759,7 @@ static inline void spimem_flash_ll_select_clk_source(uint32_t mspi_id, soc_perip
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
-#define spimem_flash_ll_select_clk_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; spimem_flash_ll_select_clk_source(__VA_ARGS__)
+#define spimem_flash_ll_select_clk_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_flash_ll_select_clk_source(__VA_ARGS__)
 
 /**
  * @brief Set FLASH core clock
@@ -768,7 +768,7 @@ static inline void spimem_flash_ll_select_clk_source(uint32_t mspi_id, soc_perip
  * @param freqdiv  Divider value
  */
 __attribute__((always_inline))
-static inline void spimem_ctrlr_ll_set_core_clock(uint8_t mspi_id, uint32_t freqdiv)
+static inline void _spimem_ctrlr_ll_set_core_clock(uint8_t mspi_id, uint32_t freqdiv)
 {
     (void)mspi_id;
     HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 1;
@@ -777,7 +777,7 @@ static inline void spimem_ctrlr_ll_set_core_clock(uint8_t mspi_id, uint32_t freq
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
-#define spimem_ctrlr_ll_set_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; spimem_ctrlr_ll_set_core_clock(__VA_ARGS__)
+#define spimem_ctrlr_ll_set_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_ctrlr_ll_set_core_clock(__VA_ARGS__)
 
 /**
  * @brief Reset whole memory spi
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1471,6 +1471,10 @@ config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
     bool
     default y
 
+config SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
+    bool
+    default y
+
 config SOC_SYSTIMER_COUNTER_NUM
     int
     default 2
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -563,6 +563,8 @@
 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED         1
 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
 
+#define SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT        1
+
 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
 #define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
 #define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
diff --git a/tools/ci/idf_pytest/constants.py b/tools/ci/idf_pytest/constants.py
@@ -123,6 +123,7 @@
     'usj_device': 'Test usb_serial_jtag and usb_serial_jtag is used as serial only (not console)',
     'twai_std': 'twai runner with all twai supported targets connect to usb-can adapter',
     'lp_i2s': 'lp_i2s runner tested with hp_i2s',
+    'ram_app': 'ram_app runners',
 }
 
 DEFAULT_CONFIG_RULES_STR = ['sdkconfig.ci=default', 'sdkconfig.ci.*=', '=default']
diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml
@@ -85,10 +85,6 @@ tools/test_apps/system/ram_loadable_app:
     - if: IDF_TARGET == "esp32c5"
       temporary: true
       reason: not supported  # TODO: [ESP32C5] IDF-8644, IDF-10315
-  disable_test:
-    - if: IDF_TARGET in ["esp32p4"]
-      temporary: true
-      reason: TBD # TODO: IDF-8994
 
 tools/test_apps/system/rtc_mem_reserve:
   enable:
diff --git a/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py b/tools/test_apps/system/ram_loadable_app/pytest_ram_loadable_app.py
@@ -4,20 +4,53 @@
 from pytest_embedded_idf.dut import IdfDut
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5'], reason='esp32p4, esp32c5 support TBD')  # TODO: [ESP32P4] IDF-8994 [ESP32C5] IDF-8644, IDF-10315
-@pytest.mark.supported_targets
+@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='esp32c5 support TBD')  # TODO: [ESP32C5] IDF-8644, IDF-10315
+@pytest.mark.esp32
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c2
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.esp32c5
+@pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize('config', ['pure_ram',], indirect=True,)
 def test_pure_ram_loadable_app(dut: IdfDut) -> None:
     dut.expect('main_task: Calling app_main()', timeout=10)
     dut.expect('Time since boot: 3 seconds...', timeout=10)
 
 
-# TODO: [ESP32P4] IDF-8994 [ESP32C5] IDF-8644, IDF-10315, [ESP32C61] IDF-10951
-@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='support TBD')
-@pytest.mark.supported_targets
+# TODO: [ESP32C5] IDF-8644, IDF-10315, [ESP32C61] IDF-10951
+@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='support TBD')
+@pytest.mark.esp32
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c2
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.esp32c5
+@pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize('config', ['defaults',], indirect=True,)
 def test_ram_loadable_app(dut: IdfDut) -> None:
     dut.expect('spi_flash: detected chip', timeout=10)
     dut.expect('Time since boot: 3 seconds...', timeout=30)
+
+
+# Tests with ram_app runners
+@pytest.mark.esp32p4
+@pytest.mark.ram_app
+@pytest.mark.parametrize('config', ['defaults',], indirect=True,)
+def test_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None:
+    dut.expect('spi_flash: detected chip', timeout=10)
+    dut.expect('Time since boot: 3 seconds...', timeout=30)
+
+
+@pytest.mark.esp32p4
+@pytest.mark.ram_app
+@pytest.mark.parametrize('config', ['pure_ram',], indirect=True,)
+def test_pure_ram_loadable_app_with_ram_app_runner(dut: IdfDut) -> None:
+    dut.expect('main_task: Calling app_main()', timeout=10)
+    dut.expect('Time since boot: 3 seconds...', timeout=10)
diff --git a/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32p4 b/tools/test_apps/system/ram_loadable_app/sdkconfig.defaults.esp32p4
@@ -0,0 +1 @@
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y

Original file line number	Diff line number	Diff line change
`@@ -109,12 +109,12 @@ static inline void bootloader_hardware_init(void)`
`109`	`109`	`REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10);`
`110`	`110`	`REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);`
`111`	`111`
	`112`	`+#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP`
`112`	`113`	`// IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used.`
`113`		`- int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));`
`114`	`114`	`if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) {`
`115`		`- spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);`
`116`		`- spimem_ctrlr_ll_set_core_clock(0, 6);`
	`115`	`+ bootloader_flash_init_core_clock();`
`117`	`116`	`}`
	`117`	`+#endif`
`118`	`118`	`}`
`119`	`119`
`120`	`120`	`static inline void bootloader_ana_reset_config(void)`
Original file line number	Diff line number	Diff line change
`@@ -123,6 +123,7 @@`
`123`	`123`	`'usj_device': 'Test usb_serial_jtag and usb_serial_jtag is used as serial only (not console)',`
`124`	`124`	`'twai_std': 'twai runner with all twai supported targets connect to usb-can adapter',`
`125`	`125`	`'lp_i2s': 'lp_i2s runner tested with hp_i2s',`
	`126`	`+ 'ram_app': 'ram_app runners',`
`126`	`127`	`}`
`127`	`128`
`128`	`129`	`DEFAULT_CONFIG_RULES_STR = ['sdkconfig.ci=default', 'sdkconfig.ci.*=', '=default']`