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test(uhci): Add tests for uhci
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‎components/esp_driver_uart/test_apps/.build-test-rules.yml‎

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@@ -32,5 +32,6 @@ components/esp_driver_uart/test_apps/uart_vfs:
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components/esp_driver_uart/test_apps/uhci:
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disable:
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- if: SOC_UHCI_SUPPORTED != 1
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- if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
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depends_components:
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- esp_driver_uart

‎components/esp_driver_uart/test_apps/uhci/CMakeLists.txt‎

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# This is the project CMakeLists.txt file for the test subproject
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cmake_minimum_required(VERSION 3.16)
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# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
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set(COMPONENTS main)
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set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components")
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include($ENV{IDF_PATH}/tools/cmake/project.cmake)
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project(uhci_test)
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if(CONFIG_COMPILER_DUMP_RTL_FILES)
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add_custom_target(check_test_app_sections ALL
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COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
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--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_uart/,${CMAKE_BINARY_DIR}/esp-idf/hal/
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--elf-file ${CMAKE_BINARY_DIR}/uhci_test.elf
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find-refs
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--from-sections=.iram0.text
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--to-sections=.flash.text,.flash.rodata
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--exit-code
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DEPENDS ${elf}
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)
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endif()
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message(STATUS "Checking uhci registers are not read-write by half-word")
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include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
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check_register_rw_half_word(SOC_MODULES "uhci" "pcr" "hp_sys_clkrst" "lpperi" "lp_clkrst"
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HAL_MODULES "uhci")

‎components/esp_driver_uart/test_apps/uhci/README.md‎

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| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-P4 | ESP32-S3 |
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| ----------------- | -------- | -------- | -------- | -------- |

‎components/esp_driver_uart/test_apps/uhci/main/CMakeLists.txt‎

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# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
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# the component can be registered as WHOLE_ARCHIVE
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idf_component_register(
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SRCS "test_app_main.c"
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"test_uhci.c"
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REQUIRES esp_driver_uart unity test_utils esp_psram
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WHOLE_ARCHIVE
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)

‎components/esp_driver_uart/test_apps/uhci/main/test_app_main.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "unity.h"
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#include "unity_test_runner.h"
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#include "unity_test_utils.h"
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#include "esp_heap_caps.h"
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#include "esp_newlib.h"
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#define TEST_MEMORY_LEAK_THRESHOLD (500)
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void setUp(void)
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{
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unity_utils_record_free_mem();
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}
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void tearDown(void)
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{
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esp_reent_cleanup(); //clean up some of the newlib's lazy allocations
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unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD);
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}
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void app_main(void)
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{
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printf(" __ __ __ __ ______ __ \n");
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printf("| | | | | | | | / || |\n");
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printf("| | | | | |__| | | ,----'| |\n");
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printf("| | | | | __ | | | | |\n");
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printf("| `--' | | | | | | `----.| |\n");
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printf(" \\______/ |__| |__| \\______||__|\n");
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unity_run_menu();
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}

‎components/esp_driver_uart/test_apps/uhci/main/test_uhci.c‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <sys/param.h>
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#include "unity.h"
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#include "test_utils.h"
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#include "driver/uart.h"
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#include "driver/uhci.h"
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#define DATA_LENGTH 1024
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#define EX_UART_NUM 1
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#define UART_TX_IO 2
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#define UART_RX_IO 3
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TEST_CASE("UHCI driver memory leaking check", "[uhci]")
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{
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uart_config_t uart_config = {
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.baud_rate = 1 * 1000 * 1000,
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.data_bits = UART_DATA_8_BITS,
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.parity = UART_PARITY_DISABLE,
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.stop_bits = UART_STOP_BITS_1,
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.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
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.source_clk = UART_SCLK_DEFAULT,
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};
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//UART parameter config
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TEST_ESP_OK(uart_param_config(EX_UART_NUM, &uart_config));
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TEST_ESP_OK(uart_set_pin(EX_UART_NUM, UART_TX_IO, UART_RX_IO, -1, -1));
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uhci_controller_config_t uhci_cfg = {
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.uart_port = EX_UART_NUM,
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.tx_trans_queue_depth = 30,
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.max_receive_internal_mem = 10 * 1024,
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.max_transmit_size = 10 * 1024,
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.dma_burst_size = 32,
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.rx_eof_flags.idle_eof = 1,
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};
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uhci_controller_handle_t uhci_ctrl;
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int size = esp_get_free_heap_size();
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for (int i = 0; i < 5; i++) {
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TEST_ESP_OK(uhci_new_controller(&uhci_cfg, &uhci_ctrl));
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vTaskDelay(10 / portTICK_PERIOD_MS);
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TEST_ESP_OK(uhci_del_controller(uhci_ctrl));
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}
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TEST_ASSERT_INT_WITHIN(300, size, esp_get_free_heap_size());
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}
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TEST_CASE("UHCI controller install-uninstall test", "[i2c]")
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{
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uhci_controller_config_t uhci_cfg = {
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.uart_port = EX_UART_NUM,
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.tx_trans_queue_depth = 30,
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.max_receive_internal_mem = 10 * 1024,
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.max_transmit_size = 10 * 1024,
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.dma_burst_size = 32,
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.rx_eof_flags.idle_eof = 1,
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};
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uhci_controller_handle_t uhci_ctrl;
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uhci_controller_handle_t uhci_ctrl2;
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TEST_ESP_OK(uhci_new_controller(&uhci_cfg, &uhci_ctrl));
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TEST_ESP_ERR(ESP_ERR_NOT_FOUND, uhci_new_controller(&uhci_cfg, &uhci_ctrl2));
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TEST_ESP_OK(uhci_del_controller(uhci_ctrl));
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}
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typedef enum {
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UHCI_EVT_PARTIAL_DATA,
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UHCI_EVT_EOF,
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} uhci_event_t;
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typedef struct {
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QueueHandle_t uhci_queue;
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size_t receive_size;
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uint8_t *p_receive_data;
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} uhci_context_t;
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static void disp_buf(uint8_t *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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printf("%02x ", buf[i]);
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if ((i + 1) % 16 == 0) {
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printf("\n");
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}
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}
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printf("\n");
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}
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IRAM_ATTR static bool s_uhci_rx_event_cbs(uhci_controller_handle_t uhci_ctrl, const uhci_rx_event_data_t *edata, void *user_ctx)
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{
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uhci_context_t *ctx = (uhci_context_t *)user_ctx;
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BaseType_t xTaskWoken = 0;
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uhci_event_t evt = 0;
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if (edata->flags.totally_received) {
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evt = UHCI_EVT_EOF;
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ctx->receive_size += edata->recv_size;
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memcpy(ctx->p_receive_data, edata->data, edata->recv_size);
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} else {
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evt = UHCI_EVT_PARTIAL_DATA;
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ctx->receive_size += edata->recv_size;
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memcpy(ctx->p_receive_data, edata->data, edata->recv_size);
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ctx->p_receive_data += edata->recv_size;
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}
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xQueueSendFromISR(ctx->uhci_queue, &evt, &xTaskWoken);
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return xTaskWoken;
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}
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static void uhci_receive_test(void *arg)
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{
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uhci_controller_handle_t uhci_ctrl = ((uhci_controller_handle_t *)arg)[0];
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SemaphoreHandle_t exit_sema = ((SemaphoreHandle_t *)arg)[1];
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uhci_context_t *ctx = calloc(1, sizeof(uhci_context_t));
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assert(ctx);
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ctx->uhci_queue = xQueueCreate(15, sizeof(uhci_event_t));
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assert(ctx->uhci_queue);
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uint8_t *receive_data = heap_caps_calloc(1, DATA_LENGTH, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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assert(receive_data);
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uint8_t *pdata = heap_caps_calloc(1, DATA_LENGTH / 4, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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assert(pdata);
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ctx->p_receive_data = receive_data;
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uhci_event_callbacks_t uhci_cbs = {
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.on_rx_trans_event = s_uhci_rx_event_cbs,
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};
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TEST_ESP_OK(uhci_register_event_callbacks(uhci_ctrl, &uhci_cbs, ctx));
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TEST_ESP_OK(uhci_receive(uhci_ctrl, pdata, DATA_LENGTH / 4));
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uhci_event_t evt;
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while (1) {
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if (xQueueReceive(ctx->uhci_queue, &evt, portMAX_DELAY) == pdTRUE) {
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if (evt == UHCI_EVT_EOF) {
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disp_buf(receive_data, ctx->receive_size);
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for (int i = 0; i < DATA_LENGTH; i++) {
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TEST_ASSERT(receive_data[i] == (uint8_t)i);
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}
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printf("Received size: %d\n", ctx->receive_size);
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break;
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}
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}
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}
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vQueueDelete(ctx->uhci_queue);
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free(pdata);
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free(receive_data);
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free(ctx);
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xSemaphoreGive(exit_sema);
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vTaskDelete(NULL);
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}
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TEST_CASE("UHCI write and receive", "[uhci]")
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{
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uart_config_t uart_config = {
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.baud_rate = 5 * 1000 * 1000,
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.data_bits = UART_DATA_8_BITS,
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.parity = UART_PARITY_DISABLE,
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.stop_bits = UART_STOP_BITS_1,
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.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
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.source_clk = UART_SCLK_XTAL,
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};
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TEST_ESP_OK(uart_param_config(EX_UART_NUM, &uart_config));
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// Connect TX and RX together for testing self send-receive
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TEST_ESP_OK(uart_set_pin(EX_UART_NUM, UART_TX_IO, UART_TX_IO, -1, -1));
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uhci_controller_config_t uhci_cfg = {
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.uart_port = EX_UART_NUM,
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.tx_trans_queue_depth = 30,
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.max_receive_internal_mem = 10 * 1024,
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.max_transmit_size = 10 * 1024,
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.dma_burst_size = 32,
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.rx_eof_flags.idle_eof = 1,
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};
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uhci_controller_handle_t uhci_ctrl;
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SemaphoreHandle_t exit_sema = xSemaphoreCreateBinary();
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TEST_ESP_OK(uhci_new_controller(&uhci_cfg, &uhci_ctrl));
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void *args[] = { uhci_ctrl, exit_sema };
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xTaskCreate(uhci_receive_test, "uhci_receive_test", 4096 * 2, args, 5, NULL);
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uint8_t data_wr[DATA_LENGTH];
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for (int i = 0; i < DATA_LENGTH; i++) {
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data_wr[i] = i;
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}
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TEST_ESP_OK(uhci_transmit(uhci_ctrl, data_wr, DATA_LENGTH));
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uhci_wait_all_tx_transaction_done(uhci_ctrl, portMAX_DELAY);
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xSemaphoreTake(exit_sema, portMAX_DELAY);
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vTaskDelay(2);
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TEST_ESP_OK(uhci_del_controller(uhci_ctrl));
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vSemaphoreDelete(exit_sema);
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}
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#if CONFIG_SPIRAM
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#if CONFIG_IDF_TARGET_ESP32S3
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static void uhci_receive_test_in_psram(void *arg)
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{
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uhci_controller_handle_t uhci_ctrl = ((uhci_controller_handle_t *)arg)[0];
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SemaphoreHandle_t exit_sema = ((SemaphoreHandle_t *)arg)[1];
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uhci_context_t *ctx = calloc(1, sizeof(uhci_context_t));
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assert(ctx);
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ctx->uhci_queue = xQueueCreate(15, sizeof(uhci_event_t));
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assert(ctx->uhci_queue);
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uint8_t *receive_data = heap_caps_calloc(1, DATA_LENGTH, MALLOC_CAP_DMA | MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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assert(receive_data);
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uint8_t *pdata = heap_caps_calloc(1, DATA_LENGTH / 4, MALLOC_CAP_DMA | MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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assert(pdata);
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ctx->p_receive_data = receive_data;
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uhci_event_callbacks_t uhci_cbs = {
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.on_rx_trans_event = s_uhci_rx_event_cbs,
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};
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TEST_ESP_OK(uhci_register_event_callbacks(uhci_ctrl, &uhci_cbs, ctx));
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TEST_ESP_OK(uhci_receive(uhci_ctrl, pdata, DATA_LENGTH / 4));
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uhci_event_t evt;
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while (1) {
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if (xQueueReceive(ctx->uhci_queue, &evt, portMAX_DELAY) == pdTRUE) {
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if (evt == UHCI_EVT_EOF) {
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disp_buf(receive_data, ctx->receive_size);
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for (int i = 0; i < DATA_LENGTH; i++) {
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TEST_ASSERT(receive_data[i] == (uint8_t)i);
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}
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printf("Received size: %d\n", ctx->receive_size);
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break;
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}
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}
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}
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vQueueDelete(ctx->uhci_queue);
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free(pdata);
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free(receive_data);
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free(ctx);
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xSemaphoreGive(exit_sema);
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vTaskDelete(NULL);
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}
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TEST_CASE("UHCI write and receive in psram", "[uhci]")
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{
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uart_config_t uart_config = {
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.baud_rate = 5 * 1000 * 1000,
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.data_bits = UART_DATA_8_BITS,
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.parity = UART_PARITY_DISABLE,
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.stop_bits = UART_STOP_BITS_1,
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.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
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.source_clk = UART_SCLK_XTAL,
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};
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TEST_ESP_OK(uart_param_config(EX_UART_NUM, &uart_config));
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// Connect TX and RX together for testing self send-receive
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TEST_ESP_OK(uart_set_pin(EX_UART_NUM, UART_TX_IO, UART_TX_IO, -1, -1));
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uhci_controller_config_t uhci_cfg = {
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.uart_port = EX_UART_NUM,
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.tx_trans_queue_depth = 30,
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.max_receive_internal_mem = 10 * 1024,
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.max_transmit_size = 10 * 1024,
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.dma_burst_size = 32,
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.rx_eof_flags.idle_eof = 1,
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};
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uhci_controller_handle_t uhci_ctrl;
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SemaphoreHandle_t exit_sema = xSemaphoreCreateBinary();
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TEST_ESP_OK(uhci_new_controller(&uhci_cfg, &uhci_ctrl));
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void *args[] = { uhci_ctrl, exit_sema };
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xTaskCreate(uhci_receive_test_in_psram, "uhci_receive_test_in_psram", 4096 * 2, args, 5, NULL);
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uint8_t *data_wr = heap_caps_calloc(1, DATA_LENGTH, MALLOC_CAP_DMA | MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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for (int i = 0; i < DATA_LENGTH; i++) {
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data_wr[i] = i;
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}
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TEST_ESP_OK(uhci_transmit(uhci_ctrl, data_wr, DATA_LENGTH));
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uhci_wait_all_tx_transaction_done(uhci_ctrl, portMAX_DELAY);
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xSemaphoreTake(exit_sema, portMAX_DELAY);
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vTaskDelay(2);
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free(data_wr);
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TEST_ESP_OK(uhci_del_controller(uhci_ctrl));
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vSemaphoreDelete(exit_sema);
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}
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#endif
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#endif // CONFIG_SPIRAM

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