Merge branch 'feat/chip_esp32c5_eco2_support_wifi' into 'master'

feat/chip esp32c5 eco2 support wifi

Closes IDF-10602, IDF-10616, IDF-10592, IDF-10590, IDF-10605, IDF-10604, IDF-10618, IDF-10617, IDF-10588, IDF-10598, IDF-10609, IDF-10610, IDF-10600, IDF-10589, IDF-10607, IDF-10608, IDF-10596, IDF-12857, IDF-11002, IDF-10601, IDF-10579, IDF-8641, IDF-8640, IDF-8639, IDF-8638, PM-403, AX-1139, AX-1151, AX-1153, AX-1155, WIFIBUG-1159, and WIFIBUG-1146

See merge request espressif/esp-idf!38566

Author: QingzhaoYin

components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c

@@ -32,14 +32,14 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
         [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(4),    I2C_ANA_MST_ANA_CONF0_REG,  0,                              I2C_MST_BBPLL_STOP_FORCE_LOW,   1, 0), .owner = ENTRY(0) },
         [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(5),    I2C_ANA_MST_ANA_CONF0_REG,  I2C_MST_BBPLL_STOP_FORCE_HIGH,  I2C_MST_BBPLL_STOP_FORCE_HIGH,  1, 0), .owner = ENTRY(0) },
         /* Clock configuration retention */
-        [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6),    PMU_CLK_STATE0_REG,         PMU_STABLE_XPD_BBPLL_STATE,     PMU_STABLE_XPD_BBPLL_STATE_M,   1, 0),  .owner = ENTRY(0)},             /* Wait PMU_WAIT_XTL_STABLE done */
-        [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(7),    PCR_AHB_FREQ_CONF_REG,      0,                              PCR_AHB_DIV_NUM,                1, 0),  .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
-        [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(8),    PCR_BUS_CLK_UPDATE_REG,     1,                              PCR_BUS_CLOCK_UPDATE,           1, 0),  .owner = ENTRY(0) | ENTRY(1) },
+        [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6),    PMU_CLK_STATE0_REG,         PMU_STABLE_XPD_BBPLL_STATE,     PMU_STABLE_XPD_BBPLL_STATE_M,   1, 0), .owner = ENTRY(0) },            /* Wait PMU_WAIT_XTL_STABLE done */
+        [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(7),    PCR_AHB_FREQ_CONF_REG,      0,                              PCR_AHB_DIV_NUM,                1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
+        [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(8),    PCR_BUS_CLK_UPDATE_REG,     1,                              PCR_BUS_CLOCK_UPDATE,           1, 0), .owner = ENTRY(0) | ENTRY(1) },
+        [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0,                              LP_ANA_PWR_GLITCH_RESET_ENA_M,  0, 1), .owner = ENTRY(0) | ENTRY(1) }, /* Disable power glitch detector on sleep backup */
+        [10] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(11), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF,                            LP_ANA_PWR_GLITCH_RESET_ENA_M,  1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Enable power glitch detector on wakeup restore */
 #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
-        [9] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(9), DR_REG_PCR_BASE,            DR_REG_PCR_BASE,    75, 0, 0,   0xffffffff, 0xffffffff, 0x200007f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
+        [11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(9), DR_REG_PCR_BASE,        DR_REG_PCR_BASE,    75, 0, 0,   0xffffffff, 0xffffffff, 0x200007f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
 #endif
-        [10] = {.config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG,      0,                      LP_ANA_PWR_GLITCH_RESET_ENA_M,  0, 1),  .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */
-        [11] = {.config = REGDMA_LINK_WRITE_INIT   (REGDMA_PCR_LINK(11), LP_ANA_POWER_GLITCH_CNTL_REG,      0xF,                    LP_ANA_PWR_GLITCH_RESET_ENA_M,  1, 0),  .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */
     };
     esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
     ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");

components/esp_hw_support/port/esp32c5/private_include/pmu_param.h

@@ -487,11 +487,11 @@ typedef struct pmu_sleep_machine_constant {
         .reset_wait_time_us             = 1,    \
         .power_supply_wait_time_us      = 2,    \
         .power_up_wait_time_us          = 2,    \
-        .regdma_s2m_work_time_us        = 275,  \
-        .regdma_s2a_work_time_us        = 587,  \
-        .regdma_m2a_work_time_us        = 320,  \
-        .regdma_a2s_work_time_us        = 494,  \
-        .regdma_rf_on_work_time_us      = 60,   \
+        .regdma_s2m_work_time_us        = 287,  \
+        .regdma_s2a_work_time_us        = 568,  \
+        .regdma_m2a_work_time_us        = 248,  \
+        .regdma_a2s_work_time_us        = 433,  \
+        .regdma_rf_on_work_time_us      = 68,   \
         .regdma_rf_off_work_time_us     = 25,   \
         .xtal_wait_stable_time_us       = 250,  \
         .pll_wait_stable_time_us        = 50    \