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Merge branch 'feature/enable_rsa_support_for_esp32h21' into 'master'
feat: enabled rsa support for esp32h21 Closes IDF-11498 See merge request espressif/esp-idf!36309
2 parents c2e9061 + a241768 commit 74d9e08

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‎components/hal/esp32h21/include/hal/mpi_ll.h‎

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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <string.h>
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#include <sys/param.h>
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#include "hal/assert.h"
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#include "hal/mpi_types.h"
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#include "soc/pcr_reg.h"
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#include "soc/pcr_struct.h"
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#include "soc/rsa_reg.h"
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#include "soc/mpi_periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enable the bus clock for MPI peripheral module
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*
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* @param enable true to enable the module, false to disable the module
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*/
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static inline void mpi_ll_enable_bus_clock(bool enable)
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{
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PCR.rsa_conf.rsa_clk_en = enable;
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}
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/**
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* @brief Reset the MPI peripheral module
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*/
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static inline void mpi_ll_reset_register(void)
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{
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PCR.rsa_conf.rsa_rst_en = 1;
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PCR.rsa_conf.rsa_rst_en = 0;
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// Clear reset on digital signature also, otherwise RSA is held in reset
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PCR.ds_conf.ds_rst_en = 0;
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PCR.ecdsa_conf.ecdsa_rst_en = 0;
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}
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static inline size_t mpi_ll_calculate_hardware_words(size_t words)
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{
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return words;
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}
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static inline void mpi_ll_power_up(void)
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{
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/* Power up the MPI peripheral */
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REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
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REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PD);
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}
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static inline void mpi_ll_power_down(void)
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{
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/* Power down the MPI peripheral */
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REG_CLR_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_FORCE_PU);
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REG_SET_BIT(PCR_RSA_PD_CTRL_REG, PCR_RSA_MEM_PD);
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}
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static inline void mpi_ll_enable_interrupt(void)
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{
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REG_WRITE(RSA_INT_ENA_REG, 1);
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}
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static inline void mpi_ll_disable_interrupt(void)
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{
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REG_WRITE(RSA_INT_ENA_REG, 0);
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}
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static inline void mpi_ll_clear_interrupt(void)
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{
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REG_WRITE(RSA_INT_CLR_REG, 1);
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}
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static inline bool mpi_ll_check_memory_init_complete(void)
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{
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return REG_READ(RSA_QUERY_CLEAN_REG) == 0;
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}
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static inline void mpi_ll_start_op(mpi_op_t op)
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{
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REG_WRITE(MPI_OPERATIONS_REG[op], 1);
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}
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static inline bool mpi_ll_get_int_status(void)
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{
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return REG_READ(RSA_QUERY_IDLE_REG) == 0;
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}
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/* Copy MPI bignum (p) to hardware memory block at 'mem_base'.
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If num_words is higher than the number of words (n) in the bignum then
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these additional words will be zeroed in the memory buffer.
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*/
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static inline void mpi_ll_write_to_mem_block(mpi_param_t param, size_t offset, const uint32_t* p, size_t n, size_t num_words)
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{
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uint32_t mem_base = MPI_BLOCK_BASES[param] + offset;
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uint32_t* pbase = (uint32_t*) mem_base;
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uint32_t copy_words = MIN(num_words, n);
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/* Copy MPI data to memory block registers */
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for (int i = 0; i < copy_words; i++) {
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pbase[i] = p[i];
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}
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/* Zero any remaining memory block data */
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for (int i = copy_words; i < num_words; i++) {
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pbase[i] = 0;
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}
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}
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static inline void mpi_ll_write_m_prime(uint32_t Mprime)
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{
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REG_WRITE(RSA_M_PRIME_REG, Mprime);
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}
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static inline void mpi_ll_write_rinv(uint32_t rinv)
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{
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REG_WRITE(MPI_BLOCK_BASES[MPI_PARAM_Z], rinv);
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}
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static inline void mpi_ll_write_at_offset(mpi_param_t param, int offset, uint32_t value)
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{
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uint32_t mem_base = MPI_BLOCK_BASES[param] + offset;
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REG_WRITE(mem_base, value);
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}
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/* Read MPI bignum (p) back from hardware memory block.
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Reads z_words words from block.
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*/
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static inline void mpi_ll_read_from_mem_block(uint32_t* p, size_t n, size_t num_words)
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{
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uint32_t mem_base = MPI_BLOCK_BASES[MPI_PARAM_Z];
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/* Copy data from memory block registers */
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const size_t REG_WIDTH = sizeof(uint32_t);
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for (size_t i = 0; i < num_words; i++) {
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p[i] = REG_READ(mem_base + (i * REG_WIDTH));
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}
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/* Zero any remaining limbs in the bignum, if the buffer is bigger
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than num_words */
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for (size_t i = num_words; i < n; i++) {
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p[i] = 0;
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}
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}
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static inline void mpi_ll_set_mode(size_t length)
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{
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REG_WRITE(RSA_MODE_REG, length);
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}
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static inline void mpi_ll_disable_constant_time(void)
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{
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REG_WRITE(RSA_CONSTANT_TIME_REG, 0);
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}
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static inline void mpi_ll_enable_constant_time(void)
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{
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REG_WRITE(RSA_CONSTANT_TIME_REG, 1);
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}
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static inline void mpi_ll_disable_search(void)
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{
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REG_WRITE(RSA_SEARCH_ENABLE_REG, 0);
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}
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static inline void mpi_ll_enable_search(void)
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{
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REG_WRITE(RSA_SEARCH_ENABLE_REG, 1);
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}
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static inline void mpi_ll_set_search_position(size_t pos)
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{
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REG_WRITE(RSA_SEARCH_POS_REG, pos);
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}
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#ifdef __cplusplus
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}
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#endif

‎components/soc/esp32h21/include/soc/Kconfig.soc_caps.in‎

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bool
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default y
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config SOC_MPI_SUPPORTED
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bool
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default y
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config SOC_ECC_SUPPORTED
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bool
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default y

‎components/soc/esp32h21/include/soc/soc_caps.h‎

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// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11578, IDF-11580
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#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11596, IDF-11598
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// #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660
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// #define SOC_MPI_SUPPORTED 1
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#define SOC_MPI_SUPPORTED 1
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// #define SOC_SHA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11501
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// #define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11495
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// #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32H21] IDF-11497

‎components/soc/esp32h21/mpi_periph.c‎

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/*
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/rsa_reg.h"
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#include "soc/mpi_periph.h"
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const uint32_t MPI_BLOCK_BASES[SOC_MPI_MEM_BLOCKS_NUM] = {
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RSA_X_MEM,
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RSA_Y_MEM,
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RSA_Z_MEM,
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RSA_M_MEM,
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};
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const uint32_t MPI_OPERATIONS_REG[SOC_MPI_OPERATIONS_NUM] = {
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RSA_SET_START_MULT_REG,
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RSA_SET_START_MODMULT_REG,
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RSA_SET_START_MODEXP_REG,
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};

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