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feat(esp32h21): support GPIO on esp32h21
1 parent 0462791 commit 760f134

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16 files changed

+357
-127
lines changed

16 files changed

+357
-127
lines changed

‎components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -535,6 +535,9 @@ TEST_CASE("GPIO_set_output_level_get_input_level_test", "[gpio]")
535535
TEST_ASSERT_EQUAL_INT_MESSAGE(1, gpio_get_level(TEST_GPIO_EXT_IN_IO), "get level error! the level should be high!");
536536
}
537537

538+
#if !CONFIG_IDF_ENV_FPGA
539+
// On FPGA do not support GPIO pull down
540+
538541
// This test routes constant-high/low signal to pins, another way is to directly connect TEST_GPIO_EXT_IN_IO to
539542
// 3.3v or GND pin
540543
TEST_CASE("GPIO_get_level_from_fixed_voltage_test", "[gpio]")
@@ -662,6 +665,8 @@ TEST_CASE("GPIO_mode_test", "[gpio]")
662665
TEST_ASSERT_EQUAL_INT_MESSAGE(!level, gpio_get_level(TEST_GPIO_EXT_IN_IO), "direction GPIO_MODE_INPUT_OUTPUT set error, it gives incorrect output");
663666
}
664667

668+
#endif //!CONFIG_IDF_ENV_FPGA
669+
665670
static void prompt_to_continue(const char *str)
666671
{
667672
printf("%s , please press \"Enter\" to go on!\n", str);

‎components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h‎

Lines changed: 17 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -10,8 +10,6 @@
1010
#include <stdbool.h>
1111
#include "soc/gpio_reg.h"
1212

13-
//TODO: [ESP32H21] IDF-11611
14-
1513
#ifdef __cplusplus
1614
extern "C" {
1715
#endif
@@ -30,7 +28,6 @@ extern "C" {
3028
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
3129
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
3230

33-
//TODO: [ESP32H21] IDF-11611, need check
3431
#define GPIO_FUNC_IN_HIGH 0x20
3532
#define GPIO_FUNC_IN_LOW 0x30
3633

@@ -50,7 +47,7 @@ typedef enum {
5047

5148

5249
/**
53-
* @brief Change GPIO(0-27) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
50+
* @brief Change GPIO(0-25) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
5451
* There is no particular ordering guaranteed; so if the order of writes is significant,
5552
* calling code should divide a single call into multiple calls.
5653
*
@@ -67,7 +64,7 @@ typedef enum {
6764
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
6865

6966
/**
70-
* @brief Sample the value of GPIO input pins(0-27) and returns a bitmask.
67+
* @brief Sample the value of GPIO input pins(0-25) and returns a bitmask.
7168
*
7269
* @param None
7370
*
@@ -76,7 +73,7 @@ void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mas
7673
uint32_t gpio_input_get(void);
7774

7875
/**
79-
* @brief Set GPIO to wakeup the ESP32.
76+
* @brief Set GPIO to wakeup the ESP32H21.
8077
* Please do not call this function in SDK.
8178
*
8279
* @param uint32_t i: gpio number.
@@ -88,7 +85,7 @@ uint32_t gpio_input_get(void);
8885
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
8986

9087
/**
91-
* @brief disable GPIOs to wakeup the ESP32.
88+
* @brief disable GPIOs to wakeup the ESP32H21.
9289
* Please do not call this function in SDK.
9390
*
9491
* @param None
@@ -100,10 +97,9 @@ void gpio_pin_wakeup_disable(void);
10097
/**
10198
* @brief set gpio input to a signal, one gpio can input to several signals.
10299
*
103-
* @param uint32_t gpio : gpio number, 0~27
104-
* gpio == 0x3C, input 0 to signal
105-
* gpio == 0x3A, input nothing to signal
106-
* gpio == 0x38, input 1 to signal
100+
* @param uint32_t gpio : gpio number, 0~25
101+
* gpio == 0x30, input 0 to signal
102+
* gpio == 0x20, input 1 to signal
107103
*
108104
* @param uint32_t signal_idx : signal index.
109105
*
@@ -116,7 +112,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
116112
/**
117113
* @brief set signal output to gpio, one signal can output to several gpios.
118114
*
119-
* @param uint32_t gpio : gpio number, 0~27
115+
* @param uint32_t gpio : gpio number, 0~25
120116
*
121117
* @param uint32_t signal_idx : signal index.
122118
* signal_idx == 0x80, cancel output put to the gpio
@@ -132,7 +128,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
132128
/**
133129
* @brief Select pad as a gpio function from IOMUX.
134130
*
135-
* @param uint32_t gpio_num : gpio number, 0~27
131+
* @param uint32_t gpio_num : gpio number, 0~25
136132
*
137133
* @return None
138134
*/
@@ -141,7 +137,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
141137
/**
142138
* @brief Set pad driver capability.
143139
*
144-
* @param uint32_t gpio_num : gpio number, 0~27
140+
* @param uint32_t gpio_num : gpio number, 0~25
145141
*
146142
* @param uint32_t drv : 0-3
147143
*
@@ -152,7 +148,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
152148
/**
153149
* @brief Pull up the pad from gpio number.
154150
*
155-
* @param uint32_t gpio_num : gpio number, 0~27
151+
* @param uint32_t gpio_num : gpio number, 0~25
156152
*
157153
* @return None
158154
*/
@@ -161,7 +157,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
161157
/**
162158
* @brief Pull down the pad from gpio number.
163159
*
164-
* @param uint32_t gpio_num : gpio number, 0~27
160+
* @param uint32_t gpio_num : gpio number, 0~25
165161
*
166162
* @return None
167163
*/
@@ -170,7 +166,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
170166
/**
171167
* @brief Unhold the pad from gpio number.
172168
*
173-
* @param uint32_t gpio_num : gpio number, 0~27
169+
* @param uint32_t gpio_num : gpio number, 0~25
174170
*
175171
* @return None
176172
*/
@@ -179,7 +175,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
179175
/**
180176
* @brief Hold the pad from gpio number.
181177
*
182-
* @param uint32_t gpio_num : gpio number, 0~27
178+
* @param uint32_t gpio_num : gpio number, 0~25
183179
*
184180
* @return None
185181
*/
@@ -188,7 +184,7 @@ void gpio_pad_hold(uint32_t gpio_num);
188184
/**
189185
* @brief enable gpio pad input.
190186
*
191-
* @param uint32_t gpio_num : gpio number, 0~27
187+
* @param uint32_t gpio_num : gpio number, 0~25
192188
*
193189
* @return None
194190
*/
@@ -197,7 +193,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
197193
/**
198194
* @brief disable gpio pad input.
199195
*
200-
* @param uint32_t gpio_num : gpio number, 0~27
196+
* @param uint32_t gpio_num : gpio number, 0~25
201197
*
202198
* @return None
203199
*/

‎components/hal/esp32h21/clk_tree_hal.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -80,10 +80,10 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
8080

8181
void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
8282
{
83-
gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
83+
abort(); // TODO: IDF-11582
8484
}
8585

8686
void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
8787
{
88-
gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
88+
abort(); // TODO: IDF-11582
8989
}

‎components/hal/esp32h21/include/hal/gpio_ll.h‎

Lines changed: 7 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,6 @@
2828
#include "hal/misc.h"
2929
#include "hal/assert.h"
3030

31-
//TODO: [ESP32H21] IDF-11611, inherit from h2
32-
3331
#ifdef __cplusplus
3432
extern "C" {
3533
#endif
@@ -116,7 +114,6 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
116114
__attribute__((always_inline))
117115
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
118116
{
119-
120117
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
121118
}
122119

@@ -309,8 +306,6 @@ __attribute__((always_inline))
309306
static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
310307
{
311308
hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
312-
// Ensure no other output signal is routed via GPIO matrix to this pin
313-
REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), SIG_GPIO_OUT_IDX);
314309
}
315310

316311
/**
@@ -356,10 +351,10 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
356351
__attribute__((always_inline))
357352
static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
358353
{
359-
// gpio_func_out_sel_cfg_reg_t reg = {
360-
// .out_sel = SIG_GPIO_OUT_IDX,
361-
// };
362-
// hw->func_out_sel_cfg[gpio_num].val = reg.val;
354+
gpio_funcn_out_sel_cfg_reg_t reg = {
355+
.funcn_out_sel = SIG_GPIO_OUT_IDX,
356+
};
357+
hw->funcn_out_sel_cfg[gpio_num].val = reg.val;
363358
}
364359

365360
/**
@@ -530,19 +525,6 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
530525
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
531526
}
532527

533-
/**
534-
* @brief Control the pin in the IOMUX
535-
*
536-
* @param bmap write mask of control value
537-
* @param val Control value
538-
* @param shift write mask shift of control value
539-
*/
540-
__attribute__((always_inline))
541-
static inline void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
542-
{
543-
SET_PERI_REG_BITS(PIN_CTRL, bmap, val, shift);
544-
}
545-
546528
/**
547529
* @brief Set clock source of IO MUX module
548530
*
@@ -554,6 +536,9 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
554536
case SOC_MOD_CLK_XTAL:
555537
PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
556538
break;
539+
case SOC_MOD_CLK_RC_FAST:
540+
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
541+
break;
557542
case SOC_MOD_CLK_PLL_F48M:
558543
PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
559544
break;

‎components/soc/esp32c5/register/soc/io_mux_reg.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,6 @@ extern "C" {
129129

130130
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
131131
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
132-
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
133132

134133
#define SPI_HD_GPIO_NUM 20
135134
#define SPI_WP_GPIO_NUM 18

‎components/soc/esp32h21/gpio_periph.c‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,11 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#include "soc/gpio_periph.h"
88

9-
//TODO: [ESP32H21] IDF-11611
10-
11-
_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
12-
139
const uint32_t GPIO_HOLD_MASK[] = {
1410
BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
1511
BIT(1), //GPIO1
@@ -37,8 +33,6 @@ const uint32_t GPIO_HOLD_MASK[] = {
3733
BIT(23), //GPIO23
3834
BIT(24), //GPIO24
3935
BIT(25), //GPIO25
40-
BIT(26), //GPIO26
41-
BIT(27), //GPIO27
4236
};
4337

4438
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

‎components/soc/esp32h21/include/soc/Kconfig.soc_caps.in‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -233,7 +233,11 @@ config SOC_GPIO_PORT
233233

234234
config SOC_GPIO_PIN_COUNT
235235
int
236-
default 28
236+
default 26
237+
238+
config SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
239+
bool
240+
default y
237241

238242
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
239243
bool
@@ -245,15 +249,19 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
245249

246250
config SOC_GPIO_IN_RANGE_MAX
247251
int
248-
default 27
252+
default 25
249253

250254
config SOC_GPIO_OUT_RANGE_MAX
251255
int
252-
default 27
256+
default 25
253257

254258
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
255259
hex
256-
default 0x000000000FFF807F
260+
default 0x0000000003FFF81F
261+
262+
config SOC_GPIO_SUPPORT_FORCE_HOLD
263+
bool
264+
default y
257265

258266
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
259267
int

‎components/soc/esp32h21/include/soc/gpio_num.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,6 @@ typedef enum {
4141
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
4242
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
4343
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
44-
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
45-
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
4644
GPIO_NUM_MAX,
4745
} gpio_num_t;
4846

‎components/soc/esp32h21/include/soc/gpio_pins.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,8 @@
1010
extern "C" {
1111
#endif
1212

13-
//TODO: [ESP32H21] IDF-11611
1413
#define GPIO_MATRIX_CONST_ONE_INPUT (0x20)
1514
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
16-
#define GPIO_MATRIX_INVALID (0x3A)
1715

1816
#ifdef __cplusplus
1917
}

‎components/soc/esp32h21/include/soc/soc_caps.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -188,17 +188,17 @@
188188

189189
/*-------------------------- GPIO CAPS ---------------------------------------*/
190190
// ESP32-H21 has 1 GPIO peripheral
191-
#define SOC_GPIO_PORT 1U
192-
#define SOC_GPIO_PIN_COUNT 28
193-
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
194-
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
195-
// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
196-
// #define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse
191+
#define SOC_GPIO_PORT 1U
192+
#define SOC_GPIO_PIN_COUNT 26
193+
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
194+
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
195+
// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
196+
#define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse
197197

198198
// GPIO peripheral has the ETM extension
199199
// #define SOC_GPIO_SUPPORT_ETM 1
200200

201-
// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins)
201+
// Target has no full LP IO subsystem, GPIO5~11 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins)
202202
// Digital IOs have their own registers to control pullup/down/capability
203203
// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers
204204
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
@@ -209,14 +209,14 @@
209209
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
210210
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
211211

212-
#define SOC_GPIO_IN_RANGE_MAX 27
213-
#define SOC_GPIO_OUT_RANGE_MAX 27
212+
#define SOC_GPIO_IN_RANGE_MAX 25
213+
#define SOC_GPIO_OUT_RANGE_MAX 25
214214

215-
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
216-
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL
215+
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~4. GPIO_NUM_12~25)
216+
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000003FFF81FULL
217217

218218
// Support to force hold all IOs
219-
// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
219+
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
220220
// Support to hold a single digital I/O when the digital domain is powered off
221221
// #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
222222

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