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Icarus113Icarus113
committed
Merge branch 'feat/h4_cache_msync' into 'master'
cache: h4 cache msync support Closes IDF-12289 See merge request espressif/esp-idf!40491
2 parents fae24cf + b25bde3 commit 7611a37

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19 files changed

+680
-144
lines changed

19 files changed

+680
-144
lines changed

‎components/esp_mm/test_apps/mm/main/test_cache_msync.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -40,12 +40,12 @@ const static char *TAG = "CACHE_TEST";
4040
#elif CONFIG_IDF_TARGET_ESP32P4
4141
#define TEST_SYNC_START (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
4242
#define TEST_SYNC_SIZE CONFIG_CACHE_L2_CACHE_SIZE
43-
#elif CONFIG_IDF_TARGET_ESP32C5
43+
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
4444
#define TEST_SYNC_START (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
4545
#define TEST_SYNC_SIZE CONFIG_CACHE_L1_CACHE_SIZE
46-
#elif CONFIG_IDF_TARGET_ESP32C61
46+
#elif CONFIG_IDF_TARGET_ESP32H4
4747
#define TEST_SYNC_START (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
48-
#define TEST_SYNC_SIZE CONFIG_CACHE_L1_CACHE_SIZE
48+
#define TEST_SYNC_SIZE CONFIG_CACHE_L1_DCACHE_SIZE
4949
#endif
5050

5151
#define RECORD_TIME_PREPARE() uint32_t __t1, __t2

‎components/esp_system/port/soc/esp32h4/Kconfig.cache‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
menu "Cache config"
2+
3+
config CACHE_L1_ICACHE_SIZE
4+
hex
5+
default 0x4000
6+
7+
config CACHE_L1_DCACHE_SIZE
8+
hex
9+
default 0x8000
10+
11+
config CACHE_L1_ICACHE_LINE_SIZE
12+
int
13+
default 32
14+
15+
config CACHE_L1_DCACHE_LINE_SIZE
16+
int
17+
default 32
18+
19+
endmenu # Cache config

‎components/hal/esp32/include/hal/cache_ll.h‎

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -100,7 +100,6 @@ __attribute__((always_inline))
100100
#endif
101101
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
102102
{
103-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
104103
cache_bus_mask_t mask = (cache_bus_mask_t)0;
105104

106105
uint32_t vaddr_end = vaddr_start + len - 1;
@@ -131,20 +130,18 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
131130
/**
132131
* Enable the Cache Buses
133132
*
134-
* @param cache_id cache ID (when l1 cache is per core)
133+
* @param bus_id bus ID
135134
* @param mask To know which buses should be enabled
136135
* @param enable 1: enable; 0: disable
137136
*/
138137
#if !BOOTLOADER_BUILD
139138
__attribute__((always_inline))
140139
#endif
141-
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
140+
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
142141
{
143142
(void) mask;
144-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
145-
146143
uint32_t bus_mask = 0;
147-
if (cache_id == 0) {
144+
if (bus_id == 0) {
148145
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
149146
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
150147
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
@@ -200,18 +197,16 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
200197
/**
201198
* Disable the Cache Buses
202199
*
203-
* @param cache_id cache ID (when l1 cache is per core)
200+
* @param bus_id bus ID
204201
* @param mask To know which buses should be enabled
205202
* @param enable 1: enable; 0: disable
206203
*/
207204
__attribute__((always_inline))
208-
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
205+
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
209206
{
210207
(void) mask;
211-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
212-
213208
uint32_t bus_mask = 0;
214-
if (cache_id == 0) {
209+
if (bus_id == 0) {
215210
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
216211
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
217212
bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);

‎components/hal/esp32c2/include/hal/cache_ll.h‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,6 @@ __attribute__((always_inline))
220220
#endif
221221
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
222222
{
223-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
224223
cache_bus_mask_t mask = (cache_bus_mask_t)0;
225224

226225
uint32_t vaddr_end = vaddr_start + len - 1;
@@ -238,15 +237,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
238237
/**
239238
* Enable the Cache Buses
240239
*
241-
* @param cache_id cache ID (when l1 cache is per core)
240+
* @param bus_id bus ID
242241
* @param mask To know which buses should be enabled
243242
*/
244243
#if !BOOTLOADER_BUILD
245244
__attribute__((always_inline))
246245
#endif
247-
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
246+
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
248247
{
249-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
250248
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
251249
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
252250

@@ -262,13 +260,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
262260
/**
263261
* Disable the Cache Buses
264262
*
265-
* @param cache_id cache ID (when l1 cache is per core)
263+
* @param bus_id bus ID
266264
* @param mask To know which buses should be disabled
267265
*/
268266
__attribute__((always_inline))
269-
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
267+
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
270268
{
271-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
272269
//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
273270
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
274271

‎components/hal/esp32c3/include/hal/cache_ll.h‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -223,7 +223,6 @@ __attribute__((always_inline))
223223
#endif
224224
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
225225
{
226-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
227226
cache_bus_mask_t mask = (cache_bus_mask_t)0;
228227

229228
uint32_t vaddr_end = vaddr_start + len - 1;
@@ -247,9 +246,8 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
247246
#if !BOOTLOADER_BUILD
248247
__attribute__((always_inline))
249248
#endif
250-
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
249+
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
251250
{
252-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
253251
//On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
254252
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
255253

@@ -269,9 +267,8 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
269267
* @param mask To know which buses should be disabled
270268
*/
271269
__attribute__((always_inline))
272-
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
270+
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
273271
{
274-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
275272
//On esp32c3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
276273
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
277274

‎components/hal/esp32c5/include/hal/cache_ll.h‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -217,7 +217,6 @@ __attribute__((always_inline))
217217
#endif
218218
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
219219
{
220-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
221220
cache_bus_mask_t mask = (cache_bus_mask_t)0;
222221

223222
uint32_t vaddr_end = vaddr_start + len - 1;
@@ -234,15 +233,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
234233
/**
235234
* Enable the Cache Buses
236235
*
237-
* @param cache_id cache ID (when l1 cache is per core)
236+
* @param bus_id bus ID
238237
* @param mask To know which buses should be enabled
239238
*/
240239
#if !BOOTLOADER_BUILD
241240
__attribute__((always_inline))
242241
#endif
243-
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
242+
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
244243
{
245-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
246244
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
247245
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
248246

@@ -258,13 +256,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
258256
/**
259257
* Disable the Cache Buses
260258
*
261-
* @param cache_id cache ID (when l1 cache is per core)
259+
* @param bus_id bus ID
262260
* @param mask To know which buses should be disabled
263261
*/
264262
__attribute__((always_inline))
265-
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
263+
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
266264
{
267-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
268265
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
269266
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
270267

‎components/hal/esp32c6/include/hal/cache_ll.h‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -198,7 +198,6 @@ __attribute__((always_inline))
198198
#endif
199199
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
200200
{
201-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
202201
cache_bus_mask_t mask = (cache_bus_mask_t)0;
203202

204203
uint32_t vaddr_end = vaddr_start + len - 1;
@@ -215,15 +214,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
215214
/**
216215
* Enable the Cache Buses
217216
*
218-
* @param cache_id cache ID (when l1 cache is per core)
217+
* @param bus_id bus ID
219218
* @param mask To know which buses should be enabled
220219
*/
221220
#if !BOOTLOADER_BUILD
222221
__attribute__((always_inline))
223222
#endif
224-
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
223+
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
225224
{
226-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
227225
//On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
228226
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
229227

@@ -239,13 +237,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
239237
/**
240238
* Disable the Cache Buses
241239
*
242-
* @param cache_id cache ID (when l1 cache is per core)
240+
* @param bus_id bus ID
243241
* @param mask To know which buses should be disabled
244242
*/
245243
__attribute__((always_inline))
246-
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
244+
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
247245
{
248-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
249246
//On esp32c6, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
250247
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
251248

‎components/hal/esp32c61/include/hal/cache_ll.h‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -216,7 +216,6 @@ __attribute__((always_inline))
216216
#endif
217217
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
218218
{
219-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
220219
cache_bus_mask_t mask = (cache_bus_mask_t)0;
221220

222221
uint32_t vaddr_end = vaddr_start + len - 1;
@@ -233,15 +232,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
233232
/**
234233
* Enable the Cache Buses
235234
*
236-
* @param cache_id cache ID (when l1 cache is per core)
235+
* @param bus_id bus ID
237236
* @param mask To know which buses should be enabled
238237
*/
239238
#if !BOOTLOADER_BUILD
240239
__attribute__((always_inline))
241240
#endif
242-
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
241+
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
243242
{
244-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
245243
//On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
246244
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
247245

@@ -257,13 +255,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
257255
/**
258256
* Disable the Cache Buses
259257
*
260-
* @param cache_id cache ID (when l1 cache is per core)
258+
* @param bus_id bus ID
261259
* @param mask To know which buses should be disabled
262260
*/
263261
__attribute__((always_inline))
264-
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
262+
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
265263
{
266-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
267264
//On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
268265
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
269266

‎components/hal/esp32h2/include/hal/cache_ll.h‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -198,7 +198,6 @@ __attribute__((always_inline))
198198
#endif
199199
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
200200
{
201-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
202201
cache_bus_mask_t mask = (cache_bus_mask_t)0;
203202

204203
uint32_t vaddr_end = vaddr_start + len - 1;
@@ -215,15 +214,14 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
215214
/**
216215
* Enable the Cache Buses
217216
*
218-
* @param cache_id cache ID (when l1 cache is per core)
217+
* @param bus_id bus ID
219218
* @param mask To know which buses should be enabled
220219
*/
221220
#if !BOOTLOADER_BUILD
222221
__attribute__((always_inline))
223222
#endif
224-
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
223+
static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
225224
{
226-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
227225
//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
228226
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
229227

@@ -239,13 +237,12 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
239237
/**
240238
* Disable the Cache Buses
241239
*
242-
* @param cache_id cache ID (when l1 cache is per core)
240+
* @param bus_id bus ID
243241
* @param mask To know which buses should be disabled
244242
*/
245243
__attribute__((always_inline))
246-
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
244+
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
247245
{
248-
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
249246
//On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
250247
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
251248

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