Skip to content

Commit 76133bc

Browse files
wancklwanckl
committed
Merge branch 'fix/remove_gpio_hal_iomux_func_sel' into 'master'
fix(driver_gpio): remove gpio_hal_iomux_func_sel See merge request espressif/esp-idf!33928
2 parents f77183c + 222b1dd commit 76133bc

File tree

19 files changed

+44
-216
lines changed

19 files changed

+44
-216
lines changed

‎components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
9393
pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
9494
// For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
9595
// flash clock signal should come from IO MUX.
96-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
96+
gpio_ll_func_sel(&GPIO, FLASH_CLK_IO, MSPI_FUNC_NUM);
9797
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
9898
} else {
9999
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
@@ -108,14 +108,14 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
108108
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
109109
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
110110
//select pin function gpio
111-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
112-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
113-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
114-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
115-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
111+
gpio_ll_func_sel(&GPIO, FLASH_SPIQ_IO, PIN_FUNC_GPIO);
112+
gpio_ll_func_sel(&GPIO, FLASH_SPID_IO, PIN_FUNC_GPIO);
113+
gpio_ll_func_sel(&GPIO, FLASH_SPIHD_IO, PIN_FUNC_GPIO);
114+
gpio_ll_func_sel(&GPIO, FLASH_SPIWP_IO, PIN_FUNC_GPIO);
115+
gpio_ll_func_sel(&GPIO, FLASH_CS_IO, PIN_FUNC_GPIO);
116116
// flash clock signal should come from IO MUX.
117+
gpio_ll_func_sel(&GPIO, FLASH_CLK_IO, MSPI_FUNC_NUM);
117118
// set drive ability for clock
118-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
119119
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
120120

121121
uint32_t flash_id = g_rom_flashchip.device_id;
@@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void)
190190
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
191191
return ESP32_PICO_V3_GPIO;
192192
default:
193-
return MSPI_IOMUX_PIN_NUM_WP;
193+
return FLASH_SPIWP_IO;
194194
}
195195
#endif
196196
}
@@ -207,7 +207,7 @@ void bootloader_configure_spi_pins(int drv)
207207
pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
208208
// For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
209209
// flash clock signal should come from IO MUX.
210-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
210+
gpio_ll_func_sel(&GPIO, FLASH_CLK_IO, MSPI_FUNC_NUM);
211211
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
212212
} else {
213213
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
@@ -222,14 +222,14 @@ void bootloader_configure_spi_pins(int drv)
222222
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
223223
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
224224
//select pin function gpio
225-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
226-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
227-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
228-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
229-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
225+
gpio_ll_func_sel(&GPIO, FLASH_SPIQ_IO, PIN_FUNC_GPIO);
226+
gpio_ll_func_sel(&GPIO, FLASH_SPID_IO, PIN_FUNC_GPIO);
227+
gpio_ll_func_sel(&GPIO, FLASH_SPIHD_IO, PIN_FUNC_GPIO);
228+
gpio_ll_func_sel(&GPIO, FLASH_SPIWP_IO, PIN_FUNC_GPIO);
229+
gpio_ll_func_sel(&GPIO, FLASH_CS_IO, PIN_FUNC_GPIO);
230230
// flash clock signal should come from IO MUX.
231+
gpio_ll_func_sel(&GPIO, FLASH_CLK_IO, MSPI_FUNC_NUM);
231232
// set drive ability for clock
232-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
233233
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
234234

235235
#if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64

‎components/esp_driver_dac/test_apps/dac/main/test_dac.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include "driver/dac_cosine.h"
1313
#include "driver/dac_continuous.h"
1414
#include "driver/gpio.h"
15+
#include "esp_private/gpio.h"
1516
#include "esp_adc/adc_oneshot.h"
1617
#include "esp_err.h"
1718
#if CONFIG_IDF_TARGET_ESP32
@@ -253,7 +254,7 @@ TEST_CASE("DAC_dma_convert_frequency_test", "[dac]")
253254
TEST_ESP_OK(pcnt_unit_enable(pcnt_unit));
254255

255256
// Connect the clock signal to pcnt input signal
256-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[GPIO_NUM_4], PIN_FUNC_GPIO);
257+
gpio_func_sel(GPIO_NUM_4, PIN_FUNC_GPIO);
257258
gpio_set_direction(GPIO_NUM_4, GPIO_MODE_INPUT_OUTPUT);
258259
// The DAC conversion frequency is equal to I2S bclk.
259260
esp_rom_gpio_connect_out_signal(GPIO_NUM_4, i2s_periph_signal[0].m_tx_ws_sig, 0, 0);

‎components/esp_driver_sdio/src/sdio_slave.c‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,7 @@ The driver of FIFOs works as below:
8989
#include "freertos/FreeRTOS.h"
9090
#include "freertos/semphr.h"
9191
#include "esp_private/periph_ctrl.h"
92+
#include "esp_private/gpio.h"
9293
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
9394
#include "esp_private/sleep_retention.h"
9495
#endif
@@ -283,15 +284,12 @@ static esp_err_t init_context(const sdio_slave_config_t *config)
283284

284285
static void configure_pin(int pin, uint32_t func, bool pullup)
285286
{
286-
const int sdmmc_func = func;
287287
const int drive_strength = 3;
288288
assert(pin != -1);
289-
uint32_t reg = GPIO_PIN_MUX_REG[pin];
290-
assert(reg != UINT32_MAX);
291289

292-
PIN_INPUT_ENABLE(reg);
293-
gpio_hal_iomux_func_sel(reg, sdmmc_func);
294-
PIN_SET_DRV(reg, drive_strength);
290+
gpio_input_enable(pin);
291+
gpio_func_sel(pin, func);
292+
gpio_set_drive_capability(pin, drive_strength);
295293
gpio_pulldown_dis(pin);
296294
if (pullup) {
297295
gpio_pullup_en(pin);
@@ -333,7 +331,7 @@ static void recover_pin(int pin, int sdio_func)
333331
int func = REG_GET_FIELD(reg, MCU_SEL);
334332
if (func == sdio_func) {
335333
gpio_set_direction(pin, GPIO_MODE_INPUT);
336-
gpio_hal_iomux_func_sel(reg, PIN_FUNC_GPIO);
334+
gpio_func_sel(pin, PIN_FUNC_GPIO);
337335
}
338336
}
339337

‎components/esp_driver_sdmmc/src/sdmmc_host.c‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include "esp_rom_gpio.h"
1818
#include "esp_rom_sys.h"
1919
#include "driver/gpio.h"
20+
#include "esp_private/gpio.h"
2021
#include "driver/sdmmc_host.h"
2122
#include "esp_private/esp_clk_tree_common.h"
2223
#include "esp_private/periph_ctrl.h"
@@ -557,16 +558,12 @@ esp_err_t sdmmc_host_init(void)
557558

558559
static void configure_pin_iomux(uint8_t gpio_num)
559560
{
560-
const int sdmmc_func = SDMMC_LL_IOMUX_FUNC;
561-
const int drive_strength = 3;
562561
assert(gpio_num != (uint8_t) GPIO_NUM_NC);
563-
gpio_pulldown_dis(gpio_num);
564562

565-
uint32_t reg = GPIO_PIN_MUX_REG[gpio_num];
566-
assert(reg != UINT32_MAX);
567-
PIN_INPUT_ENABLE(reg);
568-
gpio_hal_iomux_func_sel(reg, sdmmc_func);
569-
PIN_SET_DRV(reg, drive_strength);
563+
gpio_pulldown_dis(gpio_num);
564+
gpio_input_enable(gpio_num);
565+
gpio_iomux_output(gpio_num, SDMMC_LL_IOMUX_FUNC, false);
566+
gpio_set_drive_capability(gpio_num, 3);
570567
}
571568

572569
static void configure_pin_gpio_matrix(uint8_t gpio_num, uint8_t gpio_matrix_sig, gpio_mode_t mode, const char *name)

‎components/esp_hw_support/esp_clock_output.c‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
#include "sdkconfig.h"
99
#include "freertos/FreeRTOS.h"
1010
#include "driver/gpio.h"
11+
#include "esp_private/gpio.h"
1112
#include "esp_clock_output.h"
1213
#include "esp_check.h"
1314
#include "esp_rom_gpio.h"
@@ -140,10 +141,10 @@ static esp_clock_output_mapping_t* clkout_mapping_alloc(clkout_channel_handle_t*
140141
allocated_mapping->ref_cnt++;
141142
if (allocated_mapping->ref_cnt == 1) {
142143
#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
143-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], CLKOUT_CHANNEL_TO_IOMUX_FUNC(allocated_mapping->clkout_channel_hdl->channel_id));
144+
gpio_iomux_output(gpio_num, CLKOUT_CHANNEL_TO_IOMUX_FUNC(allocated_mapping->clkout_channel_hdl->channel_id), false);
144145
#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
145146
gpio_set_pull_mode(gpio_num, GPIO_FLOATING);
146-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
147+
gpio_func_sel(gpio_num, PIN_FUNC_GPIO);
147148
esp_rom_gpio_connect_out_signal(gpio_num, CLKOUT_CHANNEL_TO_GPIO_SIG_ID(allocated_mapping->clkout_channel_hdl->channel_id), false, false);
148149
#endif
149150
}
@@ -173,8 +174,6 @@ static void clkout_mapping_free(esp_clock_output_mapping_t *mapping_hdl)
173174
clkout_channel_free(mapping_hdl->clkout_channel_hdl);
174175
bool do_free_mapping_hdl = false;
175176
if (--mapping_hdl->ref_cnt == 0) {
176-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[mapping_hdl->mapped_io], PIN_FUNC_GPIO);
177-
esp_rom_gpio_connect_out_signal(mapping_hdl->mapped_io, SIG_GPIO_OUT_IDX, false, false);
178177
gpio_output_disable(mapping_hdl->mapped_io);
179178

180179
portENTER_CRITICAL(&mapping_hdl->clkout_channel_hdl->clkout_channel_lock);

‎components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,11 @@
88
#include "freertos/task.h"
99
#include "unity.h"
1010
#include "driver/gpio.h"
11+
#include "esp_private/gpio.h"
1112
#include "esp_err.h"
1213
#include "esp_clock_output.h"
1314
#include "hal/gpio_hal.h"
14-
15+
#include "soc/uart_pins.h"
1516
#include "soc/rtc.h"
1617

1718
#define TEST_LOOPS 100
@@ -98,8 +99,8 @@ TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]")
9899
#if CONFIG_IDF_TARGET_ESP32
99100
/* ESP32 clock out channel pin reuses UART TX/RX pin, restore its default
100101
configuration at the end of the test */
101-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD);
102-
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD);
102+
gpio_iomux_output(U0RXD_GPIO_NUM, FUNC_U0RXD_U0RXD, false);
103+
gpio_iomux_output(U0TXD_GPIO_NUM, FUNC_U0TXD_U0TXD, false);
103104
#endif
104105
}
105106

‎components/esp_psram/esp32/esp_psram_impl_quad.c‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -803,18 +803,19 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_speed_
803803
//select pin function gpio
804804
if ((psram_io->flash_clk_io == MSPI_IOMUX_PIN_NUM_CLK) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
805805
//flash clock signal should come from IO MUX.
806-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK);
806+
gpio_ll_func_sel(&GPIO, psram_io->flash_clk_io, MSPI_FUNC_NUM);
807807
} else {
808808
//flash clock signal should come from GPIO matrix.
809-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], PIN_FUNC_GPIO);
809+
gpio_ll_func_sel(&GPIO, psram_io->flash_clk_io, PIN_FUNC_GPIO);
810810
}
811-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], PIN_FUNC_GPIO);
812-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], PIN_FUNC_GPIO);
813-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], PIN_FUNC_GPIO);
814-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], PIN_FUNC_GPIO);
815-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], PIN_FUNC_GPIO);
816-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], PIN_FUNC_GPIO);
817-
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], PIN_FUNC_GPIO);
811+
812+
gpio_ll_func_sel(&GPIO, psram_io->flash_cs_io, PIN_FUNC_GPIO);
813+
gpio_ll_func_sel(&GPIO, psram_io->psram_cs_io, PIN_FUNC_GPIO);
814+
gpio_ll_func_sel(&GPIO, psram_io->psram_clk_io, PIN_FUNC_GPIO);
815+
gpio_ll_func_sel(&GPIO, psram_io->psram_spiq_sd0_io, PIN_FUNC_GPIO);
816+
gpio_ll_func_sel(&GPIO, psram_io->psram_spid_sd1_io, PIN_FUNC_GPIO);
817+
gpio_ll_func_sel(&GPIO, psram_io->psram_spihd_sd2_io, PIN_FUNC_GPIO);
818+
gpio_ll_func_sel(&GPIO, psram_io->psram_spiwp_sd3_io, PIN_FUNC_GPIO);
818819

819820
uint32_t flash_id = g_rom_flashchip.device_id;
820821
if (flash_id == FLASH_ID_GD25LQ32C) {

‎components/hal/esp32/include/hal/gpio_ll.h‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -697,18 +697,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
697697
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
698698
}
699699

700-
/**
701-
* @brief Select a function for the pin in the IOMUX
702-
*
703-
* @param pin_name Pin name to configure
704-
* @param func Function to assign to the pin
705-
*/
706-
__attribute__((always_inline))
707-
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
708-
{
709-
PIN_FUNC_SELECT(pin_name, func);
710-
}
711-
712700
/**
713701
* @brief Control the pin in the IOMUX
714702
*

‎components/hal/esp32c2/include/hal/gpio_ll.h‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -499,18 +499,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
499499
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
500500
}
501501

502-
/**
503-
* @brief Select a function for the pin in the IOMUX
504-
*
505-
* @param pin_name Pin name to configure
506-
* @param func Function to assign to the pin
507-
*/
508-
__attribute__((always_inline))
509-
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
510-
{
511-
PIN_FUNC_SELECT(pin_name, func);
512-
}
513-
514502
/**
515503
* @brief Control the pin in the IOMUX
516504
*

‎components/hal/esp32c3/include/hal/gpio_ll.h‎

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -499,22 +499,6 @@ static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_n
499499
hw->func_out_sel_cfg[gpio_num].oen_sel = !ctrl_by_periph;
500500
}
501501

502-
/**
503-
* @brief Select a function for the pin in the IOMUX
504-
*
505-
* @param pin_name Pin name to configure
506-
* @param func Function to assign to the pin
507-
*/
508-
__attribute__((always_inline))
509-
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
510-
{
511-
// Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
512-
if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
513-
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
514-
}
515-
PIN_FUNC_SELECT(pin_name, func);
516-
}
517-
518502
/**
519503
* @brief Control the pin in the IOMUX
520504
*

0 commit comments

Comments
 (0)