Skip to content

Commit 783ea76

Browse files
wancklwanckl
committed
feat(soc): c61 eco3 soc header update
1 parent c36f55c commit 783ea76

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

49 files changed

+29387
-10567
lines changed

‎components/esp_hw_support/port/esp32c61/Kconfig.hw_support‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
choice ESP32C61_REV_MIN
22
prompt "Minimum Supported ESP32-C61 Revision"
3-
default ESP32C61_REV_MIN_0
3+
default ESP32C61_REV_MIN_100
44
help
55
Required minimum chip revision. ESP-IDF will check for it and
66
reject to boot if the chip revision fails the check.
@@ -9,13 +9,13 @@ choice ESP32C61_REV_MIN
99
The complied binary will only support chips above this revision,
1010
this will also help to reduce binary size.
1111

12-
config ESP32C61_REV_MIN_0
13-
bool "Rev v0.0"
12+
config ESP32C61_REV_MIN_100
13+
bool "Rev v1.0"
1414
endchoice
1515

1616
config ESP32C61_REV_MIN_FULL
1717
int
18-
default 0 if ESP32C61_REV_MIN_0
18+
default 100 if ESP32C61_REV_MIN_100
1919

2020
config ESP_REV_MIN_FULL
2121
int
@@ -25,15 +25,15 @@ config ESP_REV_MIN_FULL
2525
# MAX Revision
2626
#
2727

28-
comment "Maximum Supported ESP32-C61 Revision (Rev v0.99)"
28+
comment "Maximum Supported ESP32-C61 Revision (Rev v1.99)"
2929
# Maximum revision that IDF supports.
3030
# It can not be changed by user.
3131
# Only Espressif can change it when a new version will be supported in IDF.
3232
# Supports all chips starting from ESP32C61_REV_MIN_FULL to ESP32C61_REV_MAX_FULL
3333

3434
config ESP32C61_REV_MAX_FULL
3535
int
36-
default 99
36+
default 199
3737
# keep in sync the "Maximum Supported Revision" description with this value
3838

3939
config ESP_REV_MAX_FULL
@@ -53,6 +53,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL
5353

5454
config ESP_EFUSE_BLOCK_REV_MAX_FULL
5555
int
56-
default 99
56+
default 199
5757
comment "Maximum Supported ESP32-C61 eFuse Block Revision (eFuse Block Rev v0.99)"
5858
# The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL

‎components/hal/esp32c61/include/hal/gpio_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ extern "C" {
3838
#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0))
3939
#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1))
4040

41-
#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE
41+
#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE
4242

4343
/**
4444
* @brief Get the configuration for an IO

‎components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
116116
int i;
117117
for (i = 0; i < (int)rd_len; i++) {
118118
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
119-
buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
119+
buf[i] = USB_SERIAL_JTAG.ep1.val;
120120
}
121121
return i;
122122
}
@@ -135,7 +135,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
135135
int i;
136136
for (i = 0; i < (int)wr_len; i++) {
137137
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
138-
USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
138+
USB_SERIAL_JTAG.ep1.val = buf[i];
139139
}
140140
return i;
141141
}

‎components/soc/esp32c61/gdma_periph.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -30,8 +30,8 @@ const gdma_signal_conn_t gdma_periph_signals = {
3030
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
3131
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
3232
33-
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
34-
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
33+
AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG
34+
AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG
3535
AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
3636
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
3737
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
@@ -40,7 +40,7 @@ const gdma_signal_conn_t gdma_periph_signals = {
4040
#define G0P0_RETENTION_REGS_CNT_0 13
4141
#define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG
4242
#define G0P0_RETENTION_REGS_CNT_1 12
43-
#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG
43+
#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG
4444
static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
4545
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
4646
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
@@ -68,8 +68,8 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
6868
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
6969
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
7070
71-
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
72-
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
71+
AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG
72+
AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG
7373
AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
7474
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
7575
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
@@ -78,7 +78,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
7878
#define G0P1_RETENTION_REGS_CNT_0 13
7979
#define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG
8080
#define G0P1_RETENTION_REGS_CNT_1 12
81-
#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG
81+
#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG
8282
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
8383
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
8484
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {

‎components/soc/esp32c61/include/soc/gpio_sig_map.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,11 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#pragma once
88

9-
// version date 2310090
109
#define EXT_ADC_START_IDX 0
1110
#define LEDC_LS_SIG_OUT0_IDX 0
1211
#define LEDC_LS_SIG_OUT1_IDX 1
@@ -141,6 +140,7 @@
141140
#define GPIO_TASK_MATRIX_OUT2_IDX 120
142141
#define GPIO_EVENT_MATRIX_IN3_IDX 121
143142
#define GPIO_TASK_MATRIX_OUT3_IDX 121
143+
#define SDIO_TOHOST_INT_OUT_IDX 124
144144
#define CLK_OUT_OUT1_IDX 126
145145
#define CLK_OUT_OUT2_IDX 127
146146
#define CLK_OUT_OUT3_IDX 128
@@ -176,5 +176,5 @@
176176
#define MODEM_DIAG29_IDX 158
177177
#define MODEM_DIAG30_IDX 159
178178
#define MODEM_DIAG31_IDX 160
179-
179+
// version date 2310090
180180
#define SIG_GPIO_OUT_IDX 256

‎components/soc/esp32c61/include/soc/interrupt_reg.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,5 +14,3 @@
1414
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
1515

1616
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG
17-
18-
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE

‎components/soc/esp32c61/include/soc/interrupts.h‎

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -35,15 +35,15 @@ typedef enum {
3535
ETS_LP_WDT_INTR_SOURCE,
3636
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
3737
ETS_LP_APM_M0_INTR_SOURCE,
38-
ETS_FROM_CPU_INTR0_SOURCE,
39-
ETS_FROM_CPU_INTR1_SOURCE,
40-
ETS_FROM_CPU_INTR2_SOURCE,
41-
ETS_FROM_CPU_INTR3_SOURCE,
38+
ETS_CPU_INTR_FROM_CPU_0_SOURCE,
39+
ETS_CPU_INTR_FROM_CPU_1_SOURCE,
40+
ETS_CPU_INTR_FROM_CPU_2_SOURCE,
41+
ETS_CPU_INTR_FROM_CPU_3_SOURCE,
4242
ETS_ASSIST_DEBUG_INTR_SOURCE,
4343
ETS_TRACE_INTR_SOURCE,
4444
ETS_CACHE_INTR_SOURCE,
4545
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
46-
ETS_GPIO_INTR_SOURCE,
46+
ETS_GPIO_INTERRUPT_PRO_SOURCE,
4747
ETS_GPIO_INTERRUPT_EXT_SOURCE,
4848
ETS_PAU_INTR_SOURCE,
4949
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
@@ -52,6 +52,8 @@ typedef enum {
5252
ETS_HP_APM_M1_INTR_SOURCE,
5353
ETS_HP_APM_M2_INTR_SOURCE,
5454
ETS_HP_APM_M3_INTR_SOURCE,
55+
ETS_CPU_APM_M0_INTR_SOURCE,
56+
ETS_CPU_APM_M1_INTR_SOURCE,
5557
ETS_MSPI_INTR_SOURCE,
5658
ETS_I2S0_INTR_SOURCE,
5759
ETS_UART0_INTR_SOURCE,
@@ -62,16 +64,18 @@ typedef enum {
6264
ETS_I2C_EXT0_INTR_SOURCE,
6365
ETS_TG0_T0_INTR_SOURCE,
6466
ETS_TG0_T1_INTR_SOURCE,
65-
ETS_TG0_WDT_LEVEL_INTR_SOURCE,
67+
ETS_TG0_WDT_INTR_SOURCE,
6668
ETS_TG1_T0_INTR_SOURCE,
6769
ETS_TG1_T1_INTR_SOURCE,
68-
ETS_TG1_WDT_LEVEL_INTR_SOURCE,
70+
ETS_TG1_WDT_INTR_SOURCE,
6971
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
7072
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
7173
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
72-
ETS_APB_ADC_INTR_SOURCE = 53,
74+
ETS_APB_ADC_INTR_SOURCE,
7375
ETS_TEMPERATURE_SENSOR_INTR_SOURCE = ETS_APB_ADC_INTR_SOURCE,
74-
ETS_DMA_IN_CH0_INTR_SOURCE = 54,
76+
ETS_SLC0_INTR_SOURCE,
77+
ETS_SLC1_INTR_SOURCE,
78+
ETS_DMA_IN_CH0_INTR_SOURCE,
7579
ETS_DMA_IN_CH1_INTR_SOURCE,
7680
ETS_DMA_OUT_CH0_INTR_SOURCE,
7781
ETS_DMA_OUT_CH1_INTR_SOURCE,

‎components/soc/esp32c61/include/soc/pmu_icg_mapping.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,11 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

77
#pragma once
8+
89
#define PMU_ICG_APB_ENA_SEC 0
910
#define PMU_ICG_APB_ENA_GDMA 1
1011
#define PMU_ICG_APB_ENA_SPI2 2
@@ -35,6 +36,7 @@
3536
#define PMU_ICG_FUNC_ENA_I2S_TX 7
3637
#define PMU_ICG_FUNC_ENA_REGDMA 8
3738
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
39+
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
3840
#define PMU_ICG_FUNC_ENA_TSENS 12
3941
#define PMU_ICG_FUNC_ENA_TG1 13
4042
#define PMU_ICG_FUNC_ENA_TG0 14

‎components/soc/esp32c61/include/soc/soc.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,7 @@
2222
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61
2323
#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
2424
#define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
25-
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61
2625
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61
27-
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE
2826

2927
//Registers Operation {{
3028
#define ETS_UNCACHED_ADDR(addr) (addr)

‎components/soc/esp32c61/include/soc/system_intr.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,10 @@
88
#include "soc/interrupts.h"
99

1010
// Maps misc system interrupt to hardware interrupt names
11-
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
12-
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_FROM_CPU_INTR1_SOURCE
13-
#define SYS_CPU_INTR_FROM_CPU_2_SOURCE ETS_FROM_CPU_INTR2_SOURCE
14-
#define SYS_CPU_INTR_FROM_CPU_3_SOURCE ETS_FROM_CPU_INTR3_SOURCE
11+
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE
12+
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_CPU_INTR_FROM_CPU_1_SOURCE
13+
#define SYS_CPU_INTR_FROM_CPU_2_SOURCE ETS_CPU_INTR_FROM_CPU_2_SOURCE
14+
#define SYS_CPU_INTR_FROM_CPU_3_SOURCE ETS_CPU_INTR_FROM_CPU_3_SOURCE
1515

16-
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
17-
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE
16+
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE
17+
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_INTR_SOURCE

0 commit comments

Comments
 (0)