Merge branch 'feat/h21_introduce_step2_3' into 'master'

feat(esp32h21): add soc register header files (stage 2/8, part 3/3)

See merge request espressif/esp-idf!35492

Author: Bruce297

components/bootloader_support/test_apps/.build-test-rules.yml

@@ -4,3 +4,7 @@ components/bootloader_support/test_apps/rtc_custom_section:
   enable:
     - if: SOC_RTC_MEM_SUPPORTED == 1
       reason: this feature is supported on chips that have RTC memory
+  disable:
+    - if: IDF_TARGET == "esp32h21"
+      temporary: true
+      reason: IDF-11534