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| 1 | +/* |
| 2 | + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +// The LL layer for ESP32-H21 LP_AON register operations |
| 8 | + |
| 9 | +#pragma once |
| 10 | + |
| 11 | +#include <stdlib.h> |
| 12 | +#include "soc/soc.h" |
| 13 | +#include "soc/lp_aon_struct.h" |
| 14 | +#include "hal/misc.h" |
| 15 | +#include "esp32h21/rom/rtc.h" |
| 16 | + |
| 17 | + |
| 18 | +#ifdef __cplusplus |
| 19 | +extern "C" { |
| 20 | +#endif |
| 21 | + |
| 22 | +/** |
| 23 | + * @brief Get ext1 wakeup source status |
| 24 | + * @return The lower 8 bits of the returned value are the bitmap of |
| 25 | + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 |
| 26 | + */ |
| 27 | +static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void) |
| 28 | +{ |
| 29 | + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_status); |
| 30 | +} |
| 31 | + |
| 32 | +/** |
| 33 | + * @brief Clear the ext1 wakeup source status |
| 34 | + */ |
| 35 | +static inline void lp_aon_ll_ext1_clear_wakeup_status(void) |
| 36 | +{ |
| 37 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_status_clr, 1); |
| 38 | +} |
| 39 | + |
| 40 | +/** |
| 41 | + * @brief Set the wake-up LP_IO of the ext1 wake-up source |
| 42 | + * @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7 |
| 43 | + * @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level |
| 44 | + * each bit's corresponding position is set to 0, the wakeup level will be low |
| 45 | + * on the contrary, each bit's corresponding position is set to 1, the wakeup |
| 46 | + * level will be high |
| 47 | + */ |
| 48 | +static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask) |
| 49 | +{ |
| 50 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, io_mask); |
| 51 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_lv, level_mask); |
| 52 | +} |
| 53 | + |
| 54 | +/** |
| 55 | + * @brief Clear all ext1 wakup-source setting |
| 56 | + */ |
| 57 | +static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) |
| 58 | +{ |
| 59 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel, 0); |
| 60 | +} |
| 61 | + |
| 62 | +/** |
| 63 | + * @brief Get ext1 wakeup source setting |
| 64 | + * @return The lower 8 bits of the returned value are the bitmap of |
| 65 | + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 |
| 66 | + */ |
| 67 | +static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) |
| 68 | +{ |
| 69 | + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, aon_ext_wakeup_sel); |
| 70 | +} |
| 71 | + |
| 72 | + |
| 73 | +/** |
| 74 | + * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. |
| 75 | + * Set the flag to inform |
| 76 | + * @param true: deepsleep false: lightsleep |
| 77 | + */ |
| 78 | +static inline void lp_aon_ll_inform_wakeup_type(bool dslp) |
| 79 | +{ |
| 80 | + if (dslp) { |
| 81 | + REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */ |
| 82 | + |
| 83 | + } else { |
| 84 | + REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */ |
| 85 | + } |
| 86 | +} |
| 87 | + |
| 88 | +/** |
| 89 | + * @brief Set the maximum number of linked lists supported by REGDMA |
| 90 | + * @param count: the maximum number of regdma link |
| 91 | + */ |
| 92 | +static inline void lp_aon_ll_set_regdma_link_count(int count) |
| 93 | +{ |
| 94 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_branch_link_length_aon, count); |
| 95 | +} |
| 96 | + |
| 97 | +/** |
| 98 | + * @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop |
| 99 | + * for some reason and the execution count exceeds this configured number, a timeout will be triggered. |
| 100 | + * @param count: the maximum number of loop |
| 101 | + */ |
| 102 | +static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count) |
| 103 | +{ |
| 104 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_work_tout_thres_aon, count); |
| 105 | +} |
| 106 | + |
| 107 | +/** |
| 108 | + * @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing |
| 109 | + * registers and gets stuck on the bus, a timeout will be triggered. |
| 110 | + * @param count: the maximum number of time |
| 111 | + */ |
| 112 | +static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count) |
| 113 | +{ |
| 114 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_backup_tout_thres_aon, count); |
| 115 | +} |
| 116 | + |
| 117 | +/** |
| 118 | + * @brief Set the regdma_link_addr |
| 119 | + * @param addr: the addr of regdma_link |
| 120 | + */ |
| 121 | +static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr) |
| 122 | +{ |
| 123 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, aon_link_addr_aon, addr); |
| 124 | +} |
| 125 | + |
| 126 | +static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count) |
| 127 | +{ |
| 128 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, aon_link_wait_tout_thres_aon, count); |
| 129 | +} |
| 130 | + |
| 131 | +static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval) |
| 132 | +{ |
| 133 | + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, aon_read_interval_aon, interval); |
| 134 | +} |
| 135 | + |
| 136 | +#ifdef __cplusplus |
| 137 | +} |
| 138 | +#endif |
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