Merge branch 'feat/support_length_eof' into 'master'

feat(uhci): Add UHCI support on esp32c5, esp32h2.

See merge request espressif/esp-idf!38794

Author: mythbuster5

components/esp_driver_uart/include/driver/uhci.h

@@ -24,6 +24,7 @@ typedef struct {
     size_t max_transmit_size;                             /*!< Maximum transfer size in one transaction, in bytes. This decides the number of DMA nodes will be used for each transaction */
     size_t max_receive_internal_mem;                      /*!< Maximum transfer size in one transaction, in bytes. Each DMA node can point to a maximum of 4096 bytes. This value determines the number of DMA nodes used for each transaction. When your transfer size is large enough, it is recommended to set this value greater than 4096 to facilitate efficient ping-pong operations, such as 10 * 1024. */
     size_t dma_burst_size;                                /*!< DMA burst size, in bytes */
+    size_t max_packet_receive;                            /*!< Max receive size, auto stop receiving after reach this value, only valid when `length_eof` set true */
 
     struct {
         uint16_t rx_brk_eof: 1;                           /*!< UHCI will end payload receive process when NULL frame is received by UART. */

components/esp_driver_uart/linker.lf

@@ -26,3 +26,5 @@ entries:
         gdma_link: gdma_link_mount_buffers (noflash)
         gdma_link: gdma_link_get_head_addr (noflash)
         gdma: gdma_start (noflash)
+        gdma: gdma_stop (noflash)
+        gdma: gdma_reset (noflash)

components/esp_driver_uart/src/uhci.c

@@ -149,6 +149,10 @@ static bool uhci_gdma_rx_callback_done(gdma_channel_handle_t dma_chan, gdma_even
             need_yield |= uhci_ctrl->rx_dir.on_rx_trans_event(uhci_ctrl, &evt_data, uhci_ctrl->user_data);
         }
 
+        // Stop the transaction when EOF is detected. In case for length EOF, there is no further more callback to be invoked.
+        gdma_stop(uhci_ctrl->rx_dir.dma_chan);
+        gdma_reset(uhci_ctrl->rx_dir.dma_chan);
+
         uhci_ctrl->rx_dir.rx_fsm = UHCI_RX_FSM_ENABLE;
     }
 
@@ -330,6 +334,7 @@ esp_err_t uhci_receive(uhci_controller_handle_t uhci_ctrl, uint8_t *read_buffer,
             }
         };
         ESP_LOGD(TAG, "The DMA node %d has %d byte", i, uhci_ctrl->rx_dir.buffer_size_per_desc_node[i]);
+        ESP_RETURN_ON_FALSE(uhci_ctrl->rx_dir.buffer_size_per_desc_node[i] != 0, ESP_ERR_INVALID_STATE, TAG, "Allocate dma node length is 0, please reconfigure the buffer_size");
         read_buffer += uhci_ctrl->rx_dir.buffer_size_per_desc_node[i];
     }
 
@@ -451,6 +456,9 @@ esp_err_t uhci_new_controller(const uhci_controller_config_t *config, uhci_contr
 
     uhci_controller_handle_t uhci_ctrl = (uhci_controller_handle_t)heap_caps_calloc(1, sizeof(uhci_controller_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
     ESP_RETURN_ON_FALSE(uhci_ctrl, ESP_ERR_NO_MEM, TAG, "no mem for uhci controller handle");
+    if (config->rx_eof_flags.length_eof) {
+        ESP_RETURN_ON_FALSE(config->max_packet_receive < UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD, ESP_ERR_INVALID_ARG, TAG, "max receive packet is over threshold");
+    }
 
     atomic_init(&uhci_ctrl->tx_dir.tx_fsm, UHCI_TX_FSM_ENABLE);
     atomic_init(&uhci_ctrl->rx_dir.rx_fsm, UHCI_TX_FSM_ENABLE);
@@ -509,6 +517,7 @@ esp_err_t uhci_new_controller(const uhci_controller_config_t *config, uhci_contr
     }
     if (config->rx_eof_flags.length_eof) {
         uhci_ll_rx_set_eof_mode(uhci_ctrl->hal.dev, UHCI_RX_LEN_EOF);
+        uhci_ll_rx_set_packet_threshold(uhci_ctrl->hal.dev, config->max_packet_receive);
     }
     if (config->rx_eof_flags.rx_brk_eof) {
         uhci_ll_rx_set_eof_mode(uhci_ctrl->hal.dev, UHCI_RX_BREAK_CHR_EOF);

components/esp_driver_uart/test_apps/.build-test-rules.yml

@@ -32,6 +32,6 @@ components/esp_driver_uart/test_apps/uart_vfs:
 components/esp_driver_uart/test_apps/uhci:
   disable:
     - if: SOC_UHCI_SUPPORTED != 1
-    - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
+    - if: CONFIG_NAME == "psram" and SOC_AHB_GDMA_SUPPORT_PSRAM != 1
   depends_components:
     - esp_driver_uart

components/esp_driver_uart/test_apps/uhci/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-P4 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_uart/test_apps/uhci/main/test_uhci.c

@@ -143,7 +143,7 @@ static void uhci_receive_test(void *arg)
         if (xQueueReceive(ctx->uhci_queue, &evt, portMAX_DELAY) == pdTRUE) {
             if (evt == UHCI_EVT_EOF) {
                 disp_buf(receive_data, ctx->receive_size);
-                for (int i = 0; i < DATA_LENGTH; i++) {
+                for (int i = 0; i < ctx->receive_size; i++) {
                     TEST_ASSERT(receive_data[i] == (uint8_t)i);
                 }
                 printf("Received size: %d\n", ctx->receive_size);
@@ -160,7 +160,7 @@ static void uhci_receive_test(void *arg)
     vTaskDelete(NULL);
 }
 
-TEST_CASE("UHCI write and receive", "[uhci]")
+TEST_CASE("UHCI write and receive with idle eof", "[uhci]")
 {
     uart_config_t uart_config = {
         .baud_rate = 5 * 1000 * 1000,
@@ -202,8 +202,51 @@ TEST_CASE("UHCI write and receive", "[uhci]")
     vSemaphoreDelete(exit_sema);
 }
 
+TEST_CASE("UHCI write and receive with length eof", "[uhci]")
+{
+    uart_config_t uart_config = {
+        .baud_rate = 5 * 1000 * 1000,
+        .data_bits = UART_DATA_8_BITS,
+        .parity = UART_PARITY_DISABLE,
+        .stop_bits = UART_STOP_BITS_1,
+        .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
+        .source_clk = UART_SCLK_XTAL,
+    };
+    TEST_ESP_OK(uart_param_config(EX_UART_NUM, &uart_config));
+    // Connect TX and RX together for testing self send-receive
+    TEST_ESP_OK(uart_set_pin(EX_UART_NUM, UART_TX_IO, UART_TX_IO, -1, -1));
+
+    uhci_controller_config_t uhci_cfg = {
+        .uart_port = EX_UART_NUM,
+        .tx_trans_queue_depth = 30,
+        .max_receive_internal_mem = 10 * 1024,
+        .max_transmit_size = 10 * 1024,
+        .dma_burst_size = 32,
+        .max_packet_receive = 100,
+        .rx_eof_flags.length_eof = 1,
+    };
+
+    uhci_controller_handle_t uhci_ctrl;
+    SemaphoreHandle_t exit_sema = xSemaphoreCreateBinary();
+    TEST_ESP_OK(uhci_new_controller(&uhci_cfg, &uhci_ctrl));
+
+    void *args[] = { uhci_ctrl, exit_sema };
+    xTaskCreate(uhci_receive_test, "uhci_receive_test", 4096 * 2, args, 5, NULL);
+
+    uint8_t data_wr[DATA_LENGTH];
+    for (int i = 0; i < DATA_LENGTH; i++) {
+        data_wr[i] = i;
+    }
+    TEST_ESP_OK(uhci_transmit(uhci_ctrl, data_wr, DATA_LENGTH));
+    uhci_wait_all_tx_transaction_done(uhci_ctrl, portMAX_DELAY);
+    xSemaphoreTake(exit_sema, portMAX_DELAY);
+    vTaskDelay(2);
+    TEST_ESP_OK(uhci_del_controller(uhci_ctrl));
+    vSemaphoreDelete(exit_sema);
+}
+
 #if CONFIG_SPIRAM
-#if CONFIG_IDF_TARGET_ESP32S3
+#if SOC_AHB_GDMA_SUPPORT_PSRAM
 static void uhci_receive_test_in_psram(void *arg)
 {
     uhci_controller_handle_t uhci_ctrl = ((uhci_controller_handle_t *)arg)[0];

components/hal/esp32c3/include/hal/uhci_ll.h

@@ -19,6 +19,7 @@ extern "C" {
 #endif
 
 #define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
+#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD  (8192)
 
 typedef enum {
     UHCI_RX_BREAK_CHR_EOF = 0x1,
@@ -159,6 +160,11 @@ static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
     }
 }
 
+static inline void uhci_ll_rx_set_packet_threshold(uhci_dev_t *hw, uint16_t length)
+{
+    hw->pkt_thres.thrs = length;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c5/include/hal/uhci_ll.h

@@ -0,0 +1,160 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for UHCI register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+#include <stdio.h>
+#include "hal/uhci_types.h"
+#include "soc/uhci_struct.h"
+#include "soc/pcr_struct.h"
+#include "hal/misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI) : (NULL))
+#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD  (8192)
+
+typedef enum {
+    UHCI_RX_BREAK_CHR_EOF = 0x1,
+    UHCI_RX_IDLE_EOF      = 0x2,
+    UHCI_RX_LEN_EOF       = 0x4,
+    UHCI_RX_EOF_MAX       = 0x7,
+} uhci_rxeof_cfg_t;
+
+/**
+ * @brief Enable the bus clock for UHCI module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void uhci_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    PCR.uhci_conf.uhci_clk_en = enable;
+}
+
+/**
+ * @brief Reset the UHCI module
+ *
+ * @param group_id Group ID
+ */
+static inline void uhci_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    PCR.uhci_conf.uhci_rst_en = 1;
+    PCR.uhci_conf.uhci_rst_en = 0;
+}
+
+static inline void uhci_ll_init(uhci_dev_t *hw)
+{
+    typeof(hw->conf0) conf0_reg;
+    conf0_reg.val = 0;
+    conf0_reg.clk_en = 1;
+    hw->conf0.val = conf0_reg.val;
+    hw->conf1.val = 0;
+}
+
+static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
+{
+    hw->conf0.uart_sel = uart_num;
+}
+
+static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
+{
+    if (seper_char->sub_chr_en) {
+        hw->conf0.seper_en = 1;
+        typeof(hw->esc_conf0) esc_conf0_reg;
+        esc_conf0_reg.val = hw->esc_conf0.val;
+
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_char, seper_char->seper_chr);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_esc_char0, seper_char->sub_chr1);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_esc_char1, seper_char->sub_chr2);
+        hw->esc_conf0.val = esc_conf0_reg.val;
+        hw->escape_conf.tx_c0_esc_en = 1;
+        hw->escape_conf.rx_c0_esc_en = 1;
+    } else {
+        hw->conf0.seper_en = 0;
+        hw->escape_conf.val = 0;
+    }
+}
+
+static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr)
+{
+    typeof(hw->escape_conf) escape_conf_reg;
+    escape_conf_reg.val = hw->escape_conf.val;
+
+    if (sub_ctr->flow_en == 1) {
+        typeof(hw->esc_conf2) esc_conf2_reg;
+        esc_conf2_reg.val = hw->esc_conf2.val;
+        typeof(hw->esc_conf3) esc_conf3_reg;
+        esc_conf3_reg.val = hw->esc_conf3.val;
+
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1, sub_ctr->xon_chr);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1_char0, sub_ctr->xon_sub1);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1_char1, sub_ctr->xon_sub2);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2, sub_ctr->xoff_chr);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2_char0, sub_ctr->xoff_sub1);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2_char1, sub_ctr->xoff_sub2);
+        escape_conf_reg.tx_11_esc_en = 1;
+        escape_conf_reg.tx_13_esc_en = 1;
+        escape_conf_reg.rx_11_esc_en = 1;
+        escape_conf_reg.rx_13_esc_en = 1;
+        hw->esc_conf2.val = esc_conf2_reg.val;
+        hw->esc_conf3.val = esc_conf3_reg.val;
+    } else {
+        escape_conf_reg.tx_11_esc_en = 0;
+        escape_conf_reg.tx_13_esc_en = 0;
+        escape_conf_reg.rx_11_esc_en = 0;
+        escape_conf_reg.rx_13_esc_en = 0;
+    }
+    hw->escape_conf.val = escape_conf_reg.val;
+}
+
+static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask)
+{
+    hw->int_ena.val |= intr_mask;
+}
+
+static inline void uhci_ll_disable_intr(uhci_dev_t *hw, uint32_t intr_mask)
+{
+    hw->int_ena.val &= (~intr_mask);
+}
+
+static inline void uhci_ll_clear_intr(uhci_dev_t *hw, uint32_t intr_mask)
+{
+    hw->int_clr.val = intr_mask;
+}
+
+static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
+{
+    return hw->int_st.val;
+}
+
+static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
+{
+    if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
+        hw->conf0.uart_rx_brk_eof_en = 1;
+    }
+    if (eof_mode & UHCI_RX_IDLE_EOF) {
+        hw->conf0.uart_idle_eof_en = 1;
+    }
+    if (eof_mode & UHCI_RX_LEN_EOF) {
+        hw->conf0.len_eof_en = 1;
+    }
+}
+
+static inline void uhci_ll_rx_set_packet_threshold(uhci_dev_t *hw, uint16_t length)
+{
+    hw->pkt_thres.pkt_thrs = length;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/uhci_ll.h

@@ -19,6 +19,7 @@ extern "C" {
 #endif
 
 #define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
+#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD  (8192)
 
 typedef enum {
     UHCI_RX_BREAK_CHR_EOF = 0x1,
@@ -151,6 +152,11 @@ static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
     }
 }
 
+static inline void uhci_ll_rx_set_packet_threshold(uhci_dev_t *hw, uint16_t length)
+{
+    hw->pkt_thres.pkt_thrs = length;
+}
+
 #ifdef __cplusplus
 }
 #endif