Merge branch 'feat/mcpwm_support_h4' into 'master'

Feat/mcpwm support h4

Closes IDF-12380 and IDF-12381

See merge request espressif/esp-idf!43003

Author: Vorrad

components/esp_driver_mcpwm/test_apps/mcpwm/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |

components/esp_hal_mcpwm/esp32c5/mcpwm_periph.c

@@ -84,7 +84,6 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
 
 /**
  * MCPWM Registers to be saved during sleep retention
- * - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
  * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
  * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
  *   |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
@@ -96,9 +95,9 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
  * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG
  * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
 */
-#define MCPWM_RETENTION_REGS_CNT 68
-#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
-static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
+#define MCPWM_RETENTION_REGS_CNT 67
+#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4)
+static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0};
 static const regdma_entries_config_t mcpwm_regs_retention[] = {
     // backup stage: save configuration registers
     // restore stage: restore the configuration registers

components/esp_hal_mcpwm/esp32c6/mcpwm_periph.c

@@ -83,7 +83,6 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
 
 /**
  * MCPWM Registers to be saved during sleep retention
- * - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
  * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
  * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
  *   |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
@@ -95,9 +94,9 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
  * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
  * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
 */
-#define MCPWM_RETENTION_REGS_CNT 61
-#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
-static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
+#define MCPWM_RETENTION_REGS_CNT 60
+#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4)
+static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0};
 static const regdma_entries_config_t mcpwm_regs_retention[] = {
     // backup stage: save configuration registers
     // restore stage: restore the configuration registers

components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c

@@ -83,7 +83,6 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
 
 /**
  * MCPWM Registers to be saved during sleep retention
- * - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
  * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
  * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
  *   |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
@@ -95,9 +94,9 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
  * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
  * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
 */
-#define MCPWM_RETENTION_REGS_CNT 61
-#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
-static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
+#define MCPWM_RETENTION_REGS_CNT 60
+#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4)
+static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0};
 static const regdma_entries_config_t mcpwm_regs_retention[] = {
     // backup stage: save configuration registers
     // restore stage: restore the configuration registers