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change(esp_hw_support): replace pmu reg operation with pmu ll layer code
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components/esp_hw_support/port/esp32h4/rtc_clk_init.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -73,10 +73,11 @@ void rtc_clk_init(rtc_clk_config_t cfg)
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REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq);
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REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.slow_clk_dcap); // h4 specific workaround (RC32K_DFREQ is used for RC_SLOW clock tuning) TODO: IDF-12313
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76-
uint32_t hp_cali_dbias = get_act_hp_dbias();
77-
uint32_t lp_cali_dbias = get_act_lp_dbias();
78-
REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias);
79-
REG_SET_FIELD(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias);
76+
uint32_t hp_dbias = get_act_hp_dbias();
77+
uint32_t lp_dbias = get_act_lp_dbias();
78+
pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, true);
79+
pmu_ll_hp_set_regulator_dbias(&PMU, PMU_MODE_HP_ACTIVE, hp_dbias);
80+
pmu_ll_lp_set_regulator_dbias(&PMU, PMU_MODE_LP_ACTIVE, lp_dbias);
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// XTAL freq can be directly informed from register field PCR_CLK_XTAL_FREQ
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