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Commit 917868d

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songruosongruo
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feat(gdma): apply c5 eco2 gdma minor modification
1 parent 7e1c430 commit 917868d

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6 files changed

+1825
-8655
lines changed

6 files changed

+1825
-8655
lines changed

‎components/hal/esp32c5/include/hal/ahb_dma_ll.h‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -26,8 +26,8 @@ extern "C" {
2626
#define GDMA_LL_RX_EVENT_MASK (0x7F)
2727
#define GDMA_LL_TX_EVENT_MASK (0x3F)
2828

29-
// any "dummy" peripheral ID can be used for M2M mode
30-
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC31)
29+
// for M2M mode, hardware will automatically assign peri_sel ID depends on the channel number (ch0: 10, ch1: 11, ch2: 12)
30+
#define AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK (0x1C00)
3131
#define AHB_DMA_LL_INVALID_PERIPH_ID (0x3F)
3232

3333
#define GDMA_LL_EVENT_TX_FIFO_UDF (1<<5)
@@ -220,6 +220,9 @@ static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
220220
case 32:
221221
burst_mode = 2; // incr8
222222
break;
223+
case 64:
224+
burst_mode = 3; // incr16
225+
break;
223226
default:
224227
HAL_ASSERT(false);
225228
break;
@@ -470,6 +473,9 @@ static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha
470473
case 32:
471474
burst_mode = 2; // incr8
472475
break;
476+
case 64:
477+
burst_mode = 3; // incr16
478+
break;
473479
default:
474480
HAL_ASSERT(false);
475481
break;

‎components/soc/esp32c5/gdma_periph.c‎

Lines changed: 25 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -34,19 +34,19 @@ const gdma_signal_conn_t gdma_periph_signals = {
3434
AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG
3535
AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG
3636
37-
AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
38-
AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
37+
AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_REG
38+
AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_REG
3939
AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
4040
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
41-
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
42-
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
41+
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
42+
AHB_DMA_MODULE_CLK_EN_REG
4343
*/
4444
#define G0P0_RETENTION_REGS_CNT_0 13
4545
#define G0P0_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x8)
46-
#define G0P0_RETENTION_REGS_CNT_1 12
46+
#define G0P0_RETENTION_REGS_CNT_1 11
4747
#define G0P0_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x2dc)
4848
static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
49-
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
49+
static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0x0c900000, 0x601, 0x0};
5050
static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
5151
[0] = {
5252
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
@@ -72,19 +72,19 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
7272
AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG
7373
AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG
7474
75-
AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
76-
AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
75+
AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_REG
76+
AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_REG
7777
AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
7878
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
79-
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
80-
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
79+
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
80+
AHB_DMA_MODULE_CLK_EN_REG
8181
*/
8282
#define G0P1_RETENTION_REGS_CNT_0 13
8383
#define G0P1_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x18)
84-
#define G0P1_RETENTION_REGS_CNT_1 12
84+
#define G0P1_RETENTION_REGS_CNT_1 11
8585
#define G0P1_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x304)
8686
static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
87-
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
87+
static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x434800, 0x18, 0x0};
8888
static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
8989
[0] = {
9090
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
@@ -107,23 +107,24 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
107107
/* AHB_DMA Channel (Group0, Pair2) Registers Context
108108
Include: AHB_DMA_MISC_CONF_REG
109109
AHB_DMA_IN_INT_ENA_CH2_REG / AHB_DMA_OUT_INT_ENA_CH2_REG
110-
111-
AHB_DMA_IN_PERI_SEL_CH2_REG / AHB_DMA_OUT_PERI_SEL_CH2_REG
110+
AHB_DMA_IN_PERI_SEL_CH2_REG
112111
AHB_DMA_IN_CONF0_CH2_REG / AHB_DMA_IN_CONF1_CH2_REG / AHB_DMA_IN_LINK_CH2_REG / AHB_DMA_IN_PRI_CH2_REG
112+
113+
AHB_DMA_OUT_PERI_SEL_CH2_REG
113114
AHB_DMA_OUT_CONF0_CH2_REG / AHB_DMA_OUT_CONF1_CH2_REG / AHB_DMA_OUT_LINK_CH2_REG / AHB_DMA_OUT_PRI_CH2_REG
114-
AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
115-
AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
115+
AHB_DMA_TX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_REG
116+
AHB_DMA_RX_CH_ARB_WEIGHT_CH2_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH2_REG
116117
AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
117118
AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
118-
AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
119-
AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
119+
AHB_DMA_ARB_TIMEOUT_REG / AHB_DMA_WEIGHT_EN_REG
120+
AHB_DMA_MODULE_CLK_EN_REG
120121
*/
121-
#define G0P2_RETENTION_REGS_CNT_0 3
122+
#define G0P2_RETENTION_REGS_CNT_0 8
122123
#define G0P2_RETENTION_MAP_BASE_0 (DR_REG_AHB_DMA_BASE + 0x28)
123-
#define G0P2_RETENTION_REGS_CNT_1 22
124-
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x1f0)
125-
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x0};
126-
static const uint32_t g0p2_regs_map1[4] = {0x13001813, 0x18, 0x18000, 0x7f26000};
124+
#define G0P2_RETENTION_REGS_CNT_1 16
125+
#define G0P2_RETENTION_MAP_BASE_1 (DR_REG_AHB_DMA_BASE + 0x250)
126+
static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x604c0000};
127+
static const uint32_t g0p2_regs_map1[4] = {0x1813, 0x1800000, 0x72600000, 0x3008};
127128
static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
128129
[0] = {
129130
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \

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