Merge branch 'refactor/rng_ll_h2' into 'master'

rng: refactor to use hal/ll apis for esp32h2

Closes IDF-12462

See merge request espressif/esp-idf!36863

Author: Icarus113

components/bootloader_support/src/bootloader_random_esp32h2.c

@@ -1,94 +1,60 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include "sdkconfig.h"
-#include "bootloader_random.h"
-#include "soc/soc.h"
-#include "soc/pcr_reg.h"
-#include "soc/apb_saradc_reg.h"
-#include "soc/pmu_reg.h"
-#include "hal/regi2c_ctrl.h"
-#include "soc/regi2c_saradc.h"
 #include "esp_log.h"
-
-static const uint32_t SAR2_CHANNEL = 9;
-static const uint32_t PATTERN_BIT_WIDTH = 6;
-static const uint32_t SAR1_ATTEN = 1;
-static const uint32_t SAR2_ATTEN = 1;
+#include "bootloader_random.h"
+#include "hal/regi2c_ctrl_ll.h"
+#include "hal/adc_ll.h"
+#include "hal/adc_types.h"
 
 void bootloader_random_enable(void)
 {
-    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
-    REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
-
-    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
-
-    REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
-
-    // select XTAL clock (40 MHz) source for ADC_CTRL_CLK
-    REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
-
-    REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
+    adc_ll_reset_register();
+    adc_ll_enable_bus_clock(true);
+    adc_ll_enable_func_clock(true);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
+    adc_ll_digi_controller_clk_div(0, 0, 0);
 
     // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
-    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
-
+    regi2c_ctrl_ll_i2c_periph_enable();
     // enable analog i2c master clock for RNG runtime
     ANALOG_CLOCK_ENABLE();
 
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1);
-
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0X08);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0X66);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0X08);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0X66);
-
-    // create patterns and set them in pattern table
-    uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN;
-    uint32_t pattern_two = SAR1_ATTEN; // we want channel 0 with max attenuation, channel doesn't really matter here
-    uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
-    REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
-
-    // set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
-    REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 0);
-
-    // Same as in C3
-    REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
-
-    // set timer expiry (timer is ADC_CTRL_CLK)
-    REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
-
-    // ENABLE_TIMER
-    REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
+    adc_ll_set_dtest_param(0);
+    adc_ll_set_ent_param(1);
+    adc_ll_enable_tout_bus(ADC_UNIT_1, true);
+    adc_ll_set_calibration_param(ADC_UNIT_1, 0x866);
+    adc_ll_set_calibration_param(ADC_UNIT_2, 0x866);
+
+    adc_digi_pattern_config_t pattern_config = {};
+    pattern_config.atten = ADC_ATTEN_DB_2_5;
+    adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
+    pattern_config.unit = ADC_UNIT_2;
+    pattern_config.atten = ADC_ATTEN_DB_2_5;
+    pattern_config.channel = ADC_CHANNEL_1;
+    adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
+    adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
+
+    adc_ll_digi_set_clk_div(15);
+    adc_ll_digi_set_trigger_interval(200);
+    adc_ll_digi_trigger_enable();
 }
 
 void bootloader_random_disable(void)
 {
-    // disable timer
-    REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
-
-    // Write reset value of this register
-    REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
-
-    // Revert ADC I2C configuration and initial voltage source setting
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_MSB, 0x60);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR2_INIT_CODE_LSB, 0x0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_MSB, 0x60);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_SAR1_INIT_CODE_LSB, 0x0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 0);
+    adc_ll_digi_trigger_disable();
+    adc_ll_digi_reset_pattern_table();
+    adc_ll_set_calibration_param(ADC_UNIT_1, 0x0);
+    adc_ll_set_calibration_param(ADC_UNIT_2, 0x0);
+    adc_ll_set_dtest_param(0);
+    adc_ll_set_ent_param(0);
+    adc_ll_enable_tout_bus(ADC_UNIT_1, false);
 
     // disable analog i2c master clock
     ANALOG_CLOCK_DISABLE();
-
-    // disable ADC_CTRL_CLK (SAR ADC function clock)
-    REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
-
-    // Set PCR_SARADC_CONF_REG to initial state
-    REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
+    adc_ll_digi_controller_clk_div(4, 0, 0);
+    adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
 }

components/hal/esp32h2/include/hal/adc_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -224,6 +224,15 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
     }
 }
 
+/**
+ * Rest pattern table to default value
+ */
+static inline void adc_ll_digi_reset_pattern_table(void)
+{
+    APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = 0xffffff;
+    APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = 0xffffff;
+}
+
 /**
  * Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
  *
@@ -659,15 +668,57 @@ static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
  * @note  Different ADC units and different attenuation options use different calibration data (initial data).
  *
  * @param adc_n ADC index number.
+ * @param param calibration param
  */
 __attribute__((always_inline))
 static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
 {
-    HAL_ASSERT(adc_n == ADC_UNIT_1);
     uint8_t msb = param >> 8;
     uint8_t lsb = param & 0xFF;
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
+
+    if (adc_n == ADC_UNIT_1) {
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
+    } else {
+        //H2 doesn't support ADC2, here is for backward compatibility for RNG
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
+    }
+}
+
+/**
+ * Set the SAR DTEST param
+ *
+ * @param param DTEST value
+ */
+__attribute__((always_inline))
+static inline void adc_ll_set_dtest_param(uint32_t param)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, param);
+}
+
+/**
+ * Set the SAR ENT param
+ *
+ * @param param ENT value
+ */
+__attribute__((always_inline))
+static inline void adc_ll_set_ent_param(uint32_t param)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, param);
+}
+
+/**
+ * Enable the SAR TOUT bus
+ *
+ * @param adc_n ADC index number.
+ * @param en true for enable
+ */
+__attribute__((always_inline))
+static inline void adc_ll_enable_tout_bus(adc_unit_t adc_n, bool en)
+{
+    HAL_ASSERT(adc_n == ADC_UNIT_1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, en);
 }
 
 /*---------------------------------------------------------------

components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include "soc/soc.h"
 #include "soc/regi2c_defs.h"
 #include "soc/i2c_ana_mst_reg.h"
+#include "soc/pmu_reg.h"
 #include "modem/modem_lpcon_struct.h"
 
 #ifdef __cplusplus
@@ -112,6 +113,22 @@ static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
     SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PD);
 }
 
+/**
+ * @brief Enable regi2c controlled periph registers
+ */
+static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
+{
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+}
+
+/**
+ * @brief Disable regi2c controlled periph registers
+ */
+static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
+{
+    CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+}
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h2/include/soc/regi2c_saradc.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,13 +30,21 @@
 #define ADC_SAR2_DREF_ADDR_MSB  0x6
 #define ADC_SAR2_DREF_ADDR_LSB  0x4
 
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR        0x1
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB    0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB    0x0
 
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR         0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB     0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB     0x0
+
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR        0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB    0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB    0x0
+
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR         0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB     0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB     0x0
 
 #define I2C_SARADC_TSENS_DAC 0x6
 #define I2C_SARADC_TSENS_DAC_MSB 3
@@ -54,22 +62,6 @@
 #define I2C_SARADC_EN_TOUT_SAR1_BUS_MSB  5
 #define I2C_SARADC_EN_TOUT_SAR1_BUS_LSB  5
 
-#define I2C_SARADC_SAR1_INIT_CODE_LSB       0
-#define I2C_SARADC_SAR1_INIT_CODE_LSB_MSB   7
-#define I2C_SARADC_SAR1_INIT_CODE_LSB_LSB   0
-
-#define I2C_SARADC_SAR1_INIT_CODE_MSB       1
-#define I2C_SARADC_SAR1_INIT_CODE_MSB_MSB   3
-#define I2C_SARADC_SAR1_INIT_CODE_MSB_LSB   0
-
-#define I2C_SARADC_SAR2_INIT_CODE_LSB       3
-#define I2C_SARADC_SAR2_INIT_CODE_LSB_MSB   7
-#define I2C_SARADC_SAR2_INIT_CODE_LSB_LSB   0
-
-#define I2C_SARADC_SAR2_INIT_CODE_MSB       4
-#define I2C_SARADC_SAR2_INIT_CODE_MSB_MSB   3
-#define I2C_SARADC_SAR2_INIT_CODE_MSB_LSB   0
-
 #define ADC_SAR1_ENCAL_GND_ADDR             0x8
 #define ADC_SAR1_ENCAL_GND_ADDR_MSB         0x1
 #define ADC_SAR1_ENCAL_GND_ADDR_LSB         0x1