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Merge branch 'feature/esp32c61_light_sleep_support_stage_3' into 'master'
feat(esp_hw_support): esp32c61 sleep support (Stage 3: support system peripheral sleep retention) Closes IDF-10384, IDF-10382, and IDF-11004 See merge request espressif/esp-idf!33298
2 parents 5d79291 + bc0404a commit 945af68

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lines changed

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+982
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lines changed

‎components/app_update/test_apps/test_app_update/pytest_app_update_ut.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ def test_app_update(dut: Dut) -> None:
2424

2525

2626
@pytest.mark.supported_targets
27-
# TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-10983
27+
# TODO: [ESP32C61] IDF-9245, IDF-10983
2828
@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C61 has not supported deep sleep')
2929
@pytest.mark.generic
3030
@pytest.mark.parametrize(

‎components/esp_hw_support/Kconfig‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -273,4 +273,13 @@ menu "Hardware Settings"
273273
config ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM
274274
bool
275275
default n
276+
277+
config ESP_CLK_RC32K_NOT_TO_USE
278+
bool
279+
default y if IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
280+
default n
281+
help
282+
Due to the poor low-temperature characteristics of
283+
RC32K (it cannot operate below -40 degrees Celsius),
284+
please avoid using it whenever possible
276285
endmenu

‎components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
1919
[0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */
2020
[1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) },
2121
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
22-
[2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 74, 0, 0, 0xffffffff, 0xffffffff, 0x7f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
22+
[2] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(2), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 75, 0, 0, 0xffffffff, 0xffffffff, 0x200007f7, 0x0), .owner = ENTRY(0) | ENTRY(1) },
2323
#endif
2424
};
2525
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);

‎components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c‎

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include "esp_private/sleep_clock.h"
8+
#include "soc/pcr_reg.h"
9+
#include "modem/modem_syscon_reg.h"
10+
11+
static const char *TAG = "sleep_clock";
12+
13+
esp_err_t sleep_clock_system_retention_init(void *arg)
14+
{
15+
const static sleep_retention_entries_config_t pcr_regs_retention[] = {
16+
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(0), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) },
17+
};
18+
19+
esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
20+
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention");
21+
ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
22+
return ESP_OK;
23+
}
24+
25+
#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
26+
esp_err_t sleep_clock_modem_retention_init(void *arg)
27+
{
28+
#define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1)
29+
30+
const static sleep_retention_entries_config_t modem_regs_retention[] = {
31+
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(0), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, N_REGS_SYSCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */
32+
};
33+
34+
esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM);
35+
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority");
36+
ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization");
37+
return ESP_OK;
38+
}
39+
#endif
40+
41+
bool clock_domain_pd_allowed(void)
42+
{
43+
const uint32_t inited_modules = sleep_retention_get_inited_modules();
44+
const uint32_t created_modules = sleep_retention_get_created_modules();
45+
const uint32_t sys_clk_dep_modules = (const uint32_t) (BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH));
46+
47+
/* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed
48+
* through MODEM_SYSCON, when one or more MODEMs are initialized, it is
49+
* necessary to check the state of CLOCK_MODEM to determine MODEM domain on
50+
* or off. The clock and reset of digital peripherals are managed through
51+
* PCR, with TOP domain similar to MODEM domain. */
52+
uint32_t modem_clk_dep_modules = 0;
53+
#if SOC_WIFI_SUPPORTED
54+
modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC) | BIT(SLEEP_RETENTION_MODULE_WIFI_BB);
55+
#endif
56+
#if SOC_BT_SUPPORTED
57+
modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
58+
#endif
59+
#if SOC_IEEE802154_SUPPORTED
60+
modem_clk_dep_modules |= BIT(SLEEP_RETENTION_MODULE_802154_MAC) | BIT(SLEEP_RETENTION_MODULE_BT_BB);
61+
#endif
62+
63+
uint32_t mask = 0;
64+
if (inited_modules & sys_clk_dep_modules) {
65+
mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
66+
}
67+
if (inited_modules & modem_clk_dep_modules) {
68+
#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED
69+
mask |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
70+
#endif
71+
}
72+
return ((inited_modules & mask) == (created_modules & mask));
73+
}
74+
75+
ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106)
76+
{
77+
sleep_retention_module_init_param_t init_param = {
78+
.cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } },
79+
.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
80+
};
81+
sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param);
82+
83+
#if CONFIG_MAC_BB_PD || CONFIG_BT_LE_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE
84+
init_param = (sleep_retention_module_init_param_t) {
85+
.cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } },
86+
.attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE
87+
};
88+
sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param);
89+
#endif
90+
return ESP_OK;
91+
}

‎components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c‎

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,162 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <stddef.h>
8+
#include <string.h>
9+
#include <inttypes.h>
10+
11+
#include "esp_attr.h"
12+
#include "esp_check.h"
13+
#include "esp_sleep.h"
14+
#include "esp_log.h"
15+
#include "esp_heap_caps.h"
16+
#include "soc/soc_caps.h"
17+
#include "sdkconfig.h"
18+
#include "soc/spi_mem_reg.h"
19+
#include "esp_private/startup_internal.h"
20+
21+
static const char *TAG = "sleep_mmu";
22+
23+
typedef struct {
24+
uint32_t start;
25+
uint32_t end;
26+
} mmu_domain_dev_regs_region_t;
27+
28+
typedef struct {
29+
mmu_domain_dev_regs_region_t *region;
30+
int region_num;
31+
uint32_t *regs_frame;
32+
} mmu_domain_dev_sleep_frame_t;
33+
34+
/**
35+
* Internal structure which holds all requested light sleep mmu retention parameters
36+
*/
37+
typedef struct {
38+
struct {
39+
mmu_domain_dev_sleep_frame_t *mmu_table_frame;
40+
} retent;
41+
} sleep_mmu_retention_t;
42+
43+
static DRAM_ATTR __attribute__((unused)) sleep_mmu_retention_t s_mmu_retention;
44+
45+
static void * mmu_domain_dev_sleep_frame_alloc_and_init(const mmu_domain_dev_regs_region_t *regions, const int region_num)
46+
{
47+
const int region_sz = sizeof(mmu_domain_dev_regs_region_t) * region_num;
48+
int regs_frame_sz = 0;
49+
for (int num = 0; num < region_num; num++) {
50+
regs_frame_sz += regions[num].end - regions[num].start;
51+
}
52+
void *frame = heap_caps_malloc(sizeof(mmu_domain_dev_sleep_frame_t) + region_sz + regs_frame_sz, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL);
53+
if (frame) {
54+
mmu_domain_dev_regs_region_t *region = (mmu_domain_dev_regs_region_t *)(frame + sizeof(mmu_domain_dev_sleep_frame_t));
55+
memcpy(region, regions, region_num * sizeof(mmu_domain_dev_regs_region_t));
56+
void *regs_frame = frame + sizeof(mmu_domain_dev_sleep_frame_t) + region_sz;
57+
memset(regs_frame, 0, regs_frame_sz);
58+
*(mmu_domain_dev_sleep_frame_t *)frame = (mmu_domain_dev_sleep_frame_t) {
59+
.region = region,
60+
.region_num = region_num,
61+
.regs_frame = (uint32_t *)regs_frame
62+
};
63+
}
64+
return frame;
65+
}
66+
67+
static inline void * mmu_domain_mmu_table_sleep_frame_alloc_and_init(void)
68+
{
69+
#define MMU_TABLE_SIZE (512 * 4)
70+
const static mmu_domain_dev_regs_region_t regions[] = {
71+
{ .start = SPI_MEM_MMU_ITEM_CONTENT_REG(0), .end = SPI_MEM_MMU_ITEM_CONTENT_REG(0) + MMU_TABLE_SIZE}
72+
};
73+
return mmu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
74+
}
75+
76+
static IRAM_ATTR void mmu_domain_dev_regs_save(mmu_domain_dev_sleep_frame_t *frame)
77+
{
78+
assert(frame);
79+
mmu_domain_dev_regs_region_t *region = frame->region;
80+
uint32_t *regs_frame = frame->regs_frame;
81+
82+
int offset = 0;
83+
for (int i = 0; i < frame->region_num; i++) {
84+
for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) {
85+
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset);
86+
regs_frame[offset++] = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
87+
}
88+
}
89+
}
90+
91+
static IRAM_ATTR void mmu_domain_dev_regs_restore(mmu_domain_dev_sleep_frame_t *frame)
92+
{
93+
assert(frame);
94+
mmu_domain_dev_regs_region_t *region = frame->region;
95+
uint32_t *regs_frame = frame->regs_frame;
96+
97+
int offset = 0;
98+
for (int i = 0; i < frame->region_num; i++) {
99+
for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) {
100+
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset);
101+
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0),regs_frame[offset++]);
102+
}
103+
}
104+
}
105+
106+
IRAM_ATTR void esp_sleep_mmu_retention(bool backup_or_restore)
107+
{
108+
if (backup_or_restore) {
109+
mmu_domain_dev_regs_save(s_mmu_retention.retent.mmu_table_frame);
110+
} else {
111+
mmu_domain_dev_regs_restore(s_mmu_retention.retent.mmu_table_frame);
112+
}
113+
}
114+
115+
static esp_err_t esp_sleep_mmu_retention_deinit_impl(void)
116+
{
117+
if (s_mmu_retention.retent.mmu_table_frame) {
118+
heap_caps_free((void *)s_mmu_retention.retent.mmu_table_frame);
119+
s_mmu_retention.retent.mmu_table_frame = NULL;
120+
}
121+
return ESP_OK;
122+
}
123+
124+
static esp_err_t esp_sleep_mmu_retention_init_impl(void)
125+
{
126+
if (s_mmu_retention.retent.mmu_table_frame == NULL) {
127+
void *frame = mmu_domain_mmu_table_sleep_frame_alloc_and_init();
128+
if (frame == NULL) {
129+
goto err;
130+
}
131+
s_mmu_retention.retent.mmu_table_frame = (mmu_domain_dev_sleep_frame_t *)frame;
132+
}
133+
return ESP_OK;
134+
err:
135+
esp_sleep_mmu_retention_deinit();
136+
return ESP_ERR_NO_MEM;
137+
}
138+
139+
esp_err_t esp_sleep_mmu_retention_init(void)
140+
{
141+
return esp_sleep_mmu_retention_init_impl();
142+
}
143+
144+
esp_err_t esp_sleep_mmu_retention_deinit(void)
145+
{
146+
return esp_sleep_mmu_retention_deinit_impl();
147+
}
148+
149+
bool mmu_domain_pd_allowed(void)
150+
{
151+
return (s_mmu_retention.retent.mmu_table_frame != NULL);
152+
}
153+
154+
ESP_SYSTEM_INIT_FN(sleep_mmu_startup_init, SECONDARY, BIT(0), 108)
155+
{
156+
esp_err_t ret;
157+
ret = esp_sleep_mmu_retention_init();
158+
if (ret != ESP_OK) {
159+
ESP_EARLY_LOGW(TAG, "Failed to enable TOP power down during light sleep.");
160+
}
161+
return ESP_OK;
162+
}

‎components/esp_hw_support/modem_clock.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -423,15 +423,15 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl
423423
esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) (
424424
(last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST :
425425
(last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL :
426-
#if !SOC_CLK_RC32K_NOT_TO_USE
426+
#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
427427
(last_src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K :
428428
#endif
429429
(last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K :
430430
ESP_PD_DOMAIN_MAX);
431431
esp_sleep_pd_domain_t pu_domain = (esp_sleep_pd_domain_t) (
432432
(src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST :
433433
(src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL :
434-
#if !SOC_CLK_RC32K_NOT_TO_USE
434+
#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
435435
(src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K :
436436
#endif
437437
(src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K :
@@ -486,7 +486,7 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module)
486486
esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) (
487487
(last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST :
488488
(last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL :
489-
#if !SOC_CLK_RC32K_NOT_TO_USE
489+
#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
490490
(last_src == MODEM_CLOCK_LPCLK_SRC_RC32K) ? ESP_PD_DOMAIN_RC32K :
491491
#endif
492492
(last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K :

‎components/esp_hw_support/port/esp32c61/CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ if(NOT BOOTLOADER_BUILD)
1717

1818
endif()
1919

20-
# TODO: [ESP32C61] IDF-9250
20+
# TODO: [ESP32C61] IDF-9304
2121
if(CONFIG_IDF_TARGET_ESP32C61)
2222
list(REMOVE_ITEM srcs
2323
"sar_periph_ctrl.c"

‎components/esp_hw_support/port/esp32c61/private_include/pmu_bit_defs.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,6 @@
1010
extern "C" {
1111
#endif
1212

13-
// TODO: IDF-9247
14-
1513
#define PMU_EXT0_WAKEUP_EN BIT(0)
1614
#define PMU_EXT1_WAKEUP_EN BIT(1)
1715
#define PMU_GPIO_WAKEUP_EN BIT(2)

‎components/esp_hw_support/port/esp32c61/private_include/pmu_param.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -476,12 +476,12 @@ typedef struct pmu_sleep_machine_constant {
476476
.reset_wait_time_us = 1, \
477477
.power_supply_wait_time_us = 20, \
478478
.power_up_wait_time_us = 2, \
479-
.regdma_s2m_work_time_us = 172, \
480-
.regdma_s2a_work_time_us = 480, \
481-
.regdma_m2a_work_time_us = 278, \
482-
.regdma_a2s_work_time_us = 382, \
483-
.regdma_rf_on_work_time_us = 70, \
484-
.regdma_rf_off_work_time_us = 23, \
479+
.regdma_s2m_work_time_us = 270, \
480+
.regdma_s2a_work_time_us = 666, \
481+
.regdma_m2a_work_time_us = 296, \
482+
.regdma_a2s_work_time_us = 586, \
483+
.regdma_rf_on_work_time_us = 138, \
484+
.regdma_rf_off_work_time_us = 28, \
485485
.xtal_wait_stable_time_us = 250, \
486486
.pll_wait_stable_time_us = 1 \
487487
} \

‎components/esp_hw_support/sleep_modes.c‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -157,8 +157,8 @@
157157
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
158158
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
159159
#elif CONFIG_IDF_TARGET_ESP32C61
160-
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
161-
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
160+
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (1148) //TODO: PM-231
161+
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (107)
162162
#elif CONFIG_IDF_TARGET_ESP32H2
163163
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (118)
164164
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9)
@@ -189,8 +189,12 @@
189189
#endif
190190

191191
#if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
192+
#if CONFIG_IDF_TARGET_ESP32C61
193+
#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1232)
194+
#elif CONFIG_IDF_TARGET_ESP32C5
192195
#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1220)
193196
#endif
197+
#endif
194198

195199
// Minimal amount of time we can sleep for
196200
#define LIGHT_SLEEP_MIN_TIME_US 200
@@ -705,7 +709,7 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
705709
#if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
706710
sleep_console_usj_pad_restore();
707711
#endif
708-
#if !CONFIG_IDF_TARGET_ESP32C61
712+
#if !CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9304
709713
sar_periph_ctrl_power_enable();
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#endif
711715
#if CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && SOC_PM_CPU_RETENTION_BY_RTCCNTL
@@ -2359,7 +2363,7 @@ static uint32_t get_power_down_flags(void)
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}
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#endif
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#if SOC_PM_SUPPORT_RC32K_PD
2362-
#if !SOC_CLK_RC32K_NOT_TO_USE
2366+
#if !CONFIG_ESP_CLK_RC32K_NOT_TO_USE
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if (s_config.domain[ESP_PD_DOMAIN_RC32K].pd_option != ESP_PD_OPTION_ON) {
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pd_flags |= PMU_SLEEP_PD_RC32K;
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}

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