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Icarus113Icarus113
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feat(psram): support fallback to use default driver pattern when id isn't match
1 parent 8fb69d6 commit 954e88c

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3 files changed

+141
-10
lines changed

3 files changed

+141
-10
lines changed

‎components/esp_psram/device/esp_psram_impl_ap_hex.c‎

Lines changed: 48 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,8 @@
4848
#define AP_HEX_PSRAM_WR_LATENCY 2
4949
#endif
5050

51-
#define AP_HEX_PSRAM_VENDOR_ID 0xD
51+
#define AP_HEX_PSRAM_VENDOR_ID_AP 0xD
52+
#define AP_HEX_PSRAM_VENDOR_ID_UNILC 0x1A //UnilC shares driver pattern with AP
5253
#define AP_HEX_PSRAM_CS_SETUP_TIME 4
5354
#define AP_HEX_PSRAM_CS_HOLD_TIME 4
5455
#define AP_HEX_PSRAM_CS_ECC_HOLD_TIME 4
@@ -60,6 +61,8 @@
6061
#define AP_HEX_PSRAM_MPLL_DEFAULT_FREQ_MHZ 400
6162
#endif
6263

64+
#define AP_HEX_PSRAM_REF_DATA 0x5a6b7c8d
65+
6366
typedef struct {
6467
union {
6568
struct {
@@ -261,6 +264,41 @@ static void s_get_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *out_reg)
261264
false);
262265
}
263266

267+
/**
268+
* Check if PSRAM is connected by write and read
269+
*/
270+
static esp_err_t s_check_psram_connected(int spi_num)
271+
{
272+
uint32_t addr = 0x80;
273+
uint32_t ref_data = AP_HEX_PSRAM_REF_DATA;
274+
uint32_t exp_data = 0;
275+
int data_bit_len = 32;
276+
277+
//write
278+
addr = 0x0;
279+
s_psram_common_transaction(spi_num,
280+
AP_HEX_PSRAM_SYNC_WRITE, AP_HEX_PSRAM_WR_CMD_BITLEN,
281+
addr, AP_HEX_PSRAM_ADDR_BITLEN,
282+
AP_HEX_PSRAM_WR_DUMMY_BITLEN,
283+
(uint8_t *)&ref_data, data_bit_len,
284+
NULL, 0,
285+
false);
286+
287+
//read MR4 and MR8
288+
s_psram_common_transaction(spi_num,
289+
AP_HEX_PSRAM_SYNC_READ, AP_HEX_PSRAM_RD_CMD_BITLEN,
290+
addr, AP_HEX_PSRAM_ADDR_BITLEN,
291+
AP_HEX_PSRAM_RD_DUMMY_BITLEN,
292+
NULL, 0,
293+
(uint8_t *)&exp_data, data_bit_len,
294+
false);
295+
296+
ESP_EARLY_LOGD(TAG, "exp_data: 0x%08x", exp_data);
297+
ESP_EARLY_LOGD(TAG, "ref_data: 0x%08x", ref_data);
298+
299+
return (exp_data == ref_data ? ESP_OK : ESP_FAIL);
300+
}
301+
264302
static void s_print_psram_info(hex_psram_mode_reg_t *reg_val)
265303
{
266304
ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id == 0x0d ? "AP" : "UNKNOWN");
@@ -411,12 +449,17 @@ esp_err_t esp_psram_impl_enable(void)
411449
mode_reg.mr8.x16 = 0;
412450
#endif
413451
s_init_psram_mode_reg(PSRAM_CTRLR_LL_MSPI_ID_3, &mode_reg);
414-
//Print PSRAM info
415-
s_get_psram_mode_reg(PSRAM_CTRLR_LL_MSPI_ID_3, &mode_reg);
416-
if (mode_reg.mr1.vendor_id != AP_HEX_PSRAM_VENDOR_ID) {
417-
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", mode_reg.mr1.vendor_id);
452+
453+
if (s_check_psram_connected(PSRAM_CTRLR_LL_MSPI_ID_3) != ESP_OK) {
454+
ESP_EARLY_LOGE(TAG, "PSRAM chip is not connected");
418455
return ESP_ERR_NOT_SUPPORTED;
419456
}
457+
458+
s_get_psram_mode_reg(PSRAM_CTRLR_LL_MSPI_ID_3, &mode_reg);
459+
if (mode_reg.mr1.vendor_id != AP_HEX_PSRAM_VENDOR_ID_AP && mode_reg.mr1.vendor_id != AP_HEX_PSRAM_VENDOR_ID_UNILC) {
460+
ESP_EARLY_LOGW(TAG, "PSRAM ID read error: 0x%08x, fallback to use default driver pattern", mode_reg.mr1.vendor_id);
461+
}
462+
420463
s_print_psram_info(&mode_reg);
421464
s_psram_size = mode_reg.mr2.density == 0x1 ? PSRAM_SIZE_4MB :
422465
mode_reg.mr2.density == 0X3 ? PSRAM_SIZE_8MB :

‎components/esp_psram/device/esp_psram_impl_ap_quad.c‎

Lines changed: 45 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@
1919
#include "esp_quad_psram_defs_ap.h"
2020
#include "soc/soc_caps.h"
2121

22+
#define AP_HEX_PSRAM_REF_DATA 0x5a6b7c8d
23+
2224
static const char* TAG = "quad_psram";
2325

2426
static uint32_t s_psram_size = 0; //this stands for physical psram size in bytes
@@ -175,6 +177,42 @@ static void psram_set_cs_timing(void)
175177
#endif
176178
}
177179

180+
/**
181+
* Check if PSRAM is connected by write and read
182+
*/
183+
static esp_err_t s_check_psram_connected(int spi_num)
184+
{
185+
uint32_t addr = 0x0;
186+
uint32_t ref_data = AP_HEX_PSRAM_REF_DATA;
187+
uint32_t exp_data = 0;
188+
int data_bit_len = 32;
189+
190+
//write
191+
psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
192+
PSRAM_QUAD_WRITE, PSRAM_QUAD_CMD_LENGTH,
193+
addr, PSRAM_QUAD_ADDR_LENGTH,
194+
0,
195+
(uint8_t *)&ref_data, data_bit_len,
196+
NULL, 0,
197+
PSRAM_LL_CS_SEL,
198+
false);
199+
200+
//read MR4 and MR8
201+
psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
202+
PSRAM_QUAD_READ, PSRAM_QUAD_CMD_LENGTH,
203+
addr, PSRAM_QUAD_ADDR_LENGTH,
204+
0,
205+
NULL, 0,
206+
(uint8_t *)&exp_data, data_bit_len,
207+
PSRAM_LL_CS_SEL,
208+
false);
209+
210+
ESP_EARLY_LOGW(TAG, "exp_data: 0x%08x", exp_data);
211+
ESP_EARLY_LOGW(TAG, "ref_data: 0x%08x", ref_data);
212+
213+
return (exp_data == ref_data ? ESP_OK : ESP_FAIL);
214+
}
215+
178216
#if CONFIG_SPIRAM_ECC_ENABLE
179217
static void s_mspi_ecc_show_info(void)
180218
{
@@ -319,6 +357,12 @@ esp_err_t esp_psram_impl_enable(void)
319357

320358
//We use SPI1 to init PSRAM
321359
psram_disable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
360+
361+
if (s_check_psram_connected(PSRAM_CTRLR_LL_MSPI_ID_1) != ESP_OK) {
362+
ESP_EARLY_LOGE(TAG, "PSRAM chip is not connected, or wrong PSRAM line mode");
363+
return ESP_ERR_NOT_SUPPORTED;
364+
}
365+
322366
psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_QUAD_ID_BITS_NUM);
323367
if (!PSRAM_QUAD_IS_VALID(psram_id)) {
324368
/* 16Mbit psram ID read error workaround:
@@ -327,8 +371,7 @@ esp_err_t esp_psram_impl_enable(void)
327371
*/
328372
psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_QUAD_ID_BITS_NUM);
329373
if (!PSRAM_QUAD_IS_VALID(psram_id)) {
330-
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)psram_id);
331-
return ESP_ERR_NOT_SUPPORTED;
374+
ESP_EARLY_LOGW(TAG, "PSRAM ID read error: 0x%08x, fallback to use default driver pattern", (uint32_t)psram_id);
332375
}
333376
}
334377
ESP_EARLY_LOGV(TAG, "MFID: 0x%x", PSRAM_QUAD_MFID(psram_id));

‎components/esp_psram/esp32s3/esp_psram_impl_octal.c‎

Lines changed: 48 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,8 @@
4545
#define OCT_PSRAM_PAGE_SIZE 2 //2 for 1024B
4646
#define OCT_PSRAM_ECC_ENABLE_MASK BIT(8)
4747

48+
#define OCT_PSRAM_REF_DATA 0x5a6b7c8d
49+
4850
typedef struct {
4951
union {
5052
struct {
@@ -222,6 +224,44 @@ static void s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *out_reg)
222224
false);
223225
}
224226

227+
/**
228+
* Check if PSRAM is connected by write and read
229+
*/
230+
static esp_err_t s_check_psram_connected(int spi_num)
231+
{
232+
esp_rom_spiflash_read_mode_t mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
233+
int cmd_len = OCT_PSRAM_WR_CMD_BITLEN;
234+
uint32_t addr = 0x0;
235+
int addr_bit_len = OCT_PSRAM_ADDR_BITLEN;
236+
uint32_t ref_data = OCT_PSRAM_REF_DATA;
237+
uint32_t exp_data = 0;
238+
int data_bit_len = 32;
239+
240+
//write
241+
esp_rom_opiflash_exec_cmd(spi_num, mode,
242+
OPI_PSRAM_SYNC_WRITE, cmd_len,
243+
addr, addr_bit_len,
244+
OCT_PSRAM_WR_DUMMY_BITLEN,
245+
(uint8_t *)&ref_data, data_bit_len,
246+
NULL, 0,
247+
BIT(1),
248+
false);
249+
//read
250+
esp_rom_opiflash_exec_cmd(spi_num, mode,
251+
OPI_PSRAM_SYNC_READ, cmd_len,
252+
addr, addr_bit_len,
253+
OCT_PSRAM_RD_DUMMY_BITLEN,
254+
NULL, 0,
255+
(uint8_t *)&exp_data, data_bit_len,
256+
BIT(1),
257+
false);
258+
259+
ESP_EARLY_LOGD(TAG, "exp_data: 0x%08x", exp_data);
260+
ESP_EARLY_LOGD(TAG, "ref_data: 0x%08x", ref_data);
261+
262+
return (exp_data == ref_data ? ESP_OK : ESP_FAIL);
263+
}
264+
225265
static void s_print_psram_info(opi_psram_mode_reg_t *reg_val)
226266
{
227267
ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id == 0x0d ? "AP" : (reg_val->mr1.vendor_id == 0x1a ? "UnilC" : "UNKNOWN"));
@@ -316,12 +356,17 @@ esp_err_t esp_psram_impl_enable(void)
316356
mode_reg.mr8.bl = 3;
317357
mode_reg.mr8.bt = 0;
318358
s_init_psram_mode_reg(1, &mode_reg);
319-
//Print PSRAM info
359+
360+
if (s_check_psram_connected(1) != ESP_OK) {
361+
ESP_EARLY_LOGE(TAG, "PSRAM chip is not connected, or wrong PSRAM line mode");
362+
return ESP_ERR_NOT_SUPPORTED;
363+
}
364+
320365
s_get_psram_mode_reg(1, &mode_reg);
321366
if (mode_reg.mr1.vendor_id != OCT_PSRAM_VENDOR_ID_AP && mode_reg.mr1.vendor_id != OCT_PSRAM_VENDOR_ID_UNILC) {
322-
ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", mode_reg.mr1.vendor_id);
323-
return ESP_ERR_NOT_SUPPORTED;
367+
ESP_EARLY_LOGW(TAG, "PSRAM ID read error: 0x%08x, fallback to use default driver pattern", mode_reg.mr1.vendor_id);
324368
}
369+
325370
s_print_psram_info(&mode_reg);
326371
s_psram_size = mode_reg.mr2.density == 0x1 ? PSRAM_SIZE_4MB :
327372
mode_reg.mr2.density == 0X3 ? PSRAM_SIZE_8MB :

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