Merge branch 'ci/tee_apm_pms_test_app' into 'master'

ci(hal): Add HAL/LL-based test app for the TEE and APM peripherals

Closes IDF-8614, IDF-8615, IDF-9229, IDF-9230, IDF-10422, IDF-12646, IDF-12647, IDF-12648, IDF-12649, and IDF-12877

See merge request espressif/esp-idf!39873

Author: laukik-hase

.gitlab/CODEOWNERS

@@ -125,6 +125,7 @@
 /components/freertos/                 @esp-idf-codeowners/system
 /components/hal/                      @esp-idf-codeowners/peripherals
 /components/hal/test_apps/crypto/     @esp-idf-codeowners/peripherals @esp-idf-codeowners/security
+/components/hal/test_apps/tee_apm/    @esp-idf-codeowners/peripherals @esp-idf-codeowners/security
 /components/heap/                     @esp-idf-codeowners/system
 /components/http_parser/              @esp-idf-codeowners/app-utilities
 /components/idf_test/                 @esp-idf-codeowners/peripherals @esp-idf-codeowners/system

components/esp_hw_support/port/esp32c5/cpu_region_protect.c

@@ -136,6 +136,7 @@ void esp_cpu_configure_region_protection(void)
     _Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
 
     // 2. I/D-ROM
+#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
     const uint32_t drom_start = (uint32_t) (ets_rom_layout_p->drom_start);
     if ((drom_start & (SOC_CPU_PMP_REGION_GRANULARITY - 1)) == 0) {
         // We can skip configuring the PMP entry for the [SOC_IROM_MASK_LOW - drom_start]
@@ -144,9 +145,11 @@ void esp_cpu_configure_region_protection(void)
         // the region as cacheable. Thus, we save on one PMP entry.
         PMP_ENTRY_SET(1, drom_start, NONE);
         PMP_ENTRY_SET(2, SOC_DROM_MASK_HIGH, PMP_TOR | R);
-    } else {
+    } else
+#endif
+    {
         PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
-        PMP_ENTRY_SET(2, SOC_IROM_MASK_HIGH, PMP_TOR | RX);
+        PMP_ENTRY_SET(2, SOC_IROM_MASK_HIGH, PMP_TOR | CONDITIONAL_RX);
         _Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I/D-ROM region");
     }
 

components/esp_hw_support/port/esp32c61/cpu_region_protect.c

@@ -133,14 +133,17 @@ void esp_cpu_configure_region_protection(void)
     _Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
 
     // 2. I/D-ROM
+#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
     const uint32_t drom_start = (uint32_t) (ets_rom_layout_p->drom_start);
     if ((drom_start & (SOC_CPU_PMP_REGION_GRANULARITY - 1)) == 0) {
         PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
         PMP_ENTRY_SET(2, drom_start, PMP_TOR | RX);
         PMP_ENTRY_SET(3, SOC_DROM_MASK_HIGH, PMP_TOR | RW);
-    } else {
+    } else
+#endif
+    {
         const uint32_t pmpaddr1 = PMPADDR_NAPOT(SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH);
-        PMP_ENTRY_SET(1, pmpaddr1, PMP_NAPOT | RX);
+        PMP_ENTRY_SET(1, pmpaddr1, PMP_NAPOT | CONDITIONAL_RX);
         _Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I/D-ROM region");
     }
 

components/hal/.build-test-rules.yml

@@ -11,3 +11,7 @@ components/hal/test_apps/hal_i2c:
 components/hal/test_apps/hal_utils:
   enable:
     - if: IDF_TARGET == "linux"
+
+components/hal/test_apps/tee_apm:
+  disable:
+    - if: IDF_TARGET not in ["esp32c6", "esp32h2", "esp32c5", "esp32c61"]

components/hal/apm_hal.c

@@ -218,9 +218,84 @@ void apm_hal_enable_region_filter(apm_ctrl_module_t ctrl_mod, uint32_t regn_num,
     }
 }
 
+void apm_hal_set_region_start_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr)
+{
+    switch (ctrl_mod) {
+        case APM_CTRL_HP_APM:
+            apm_ll_hp_apm_set_region_start_addr(regn_num, addr);
+            break;
+#if SOC_APM_LP_APM0_SUPPORTED
+        case APM_CTRL_LP_APM0:
+            apm_ll_lp_apm0_set_region_start_addr(regn_num, addr);
+            break;
+#endif
+        case APM_CTRL_LP_APM:
+            apm_ll_lp_apm_set_region_start_addr(regn_num, addr);
+            break;
+#if SOC_APM_CPU_APM_SUPPORTED
+        case APM_CTRL_CPU_APM:
+            apm_ll_cpu_apm_set_region_start_addr(regn_num, addr);
+            break;
+#endif
+        default:
+            break;
+    }
+}
+
+void apm_hal_set_region_end_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr)
+{
+    switch (ctrl_mod) {
+        case APM_CTRL_HP_APM:
+            apm_ll_hp_apm_set_region_end_addr(regn_num, addr);
+            break;
+#if SOC_APM_LP_APM0_SUPPORTED
+        case APM_CTRL_LP_APM0:
+            apm_ll_lp_apm0_set_region_end_addr(regn_num, addr);
+            break;
+#endif
+        case APM_CTRL_LP_APM:
+            apm_ll_lp_apm_set_region_end_addr(regn_num, addr);
+            break;
+#if SOC_APM_CPU_APM_SUPPORTED
+        case APM_CTRL_CPU_APM:
+            apm_ll_cpu_apm_set_region_end_addr(regn_num, addr);
+            break;
+#endif
+        default:
+            break;
+    }
+}
+
+void apm_hal_set_sec_mode_region_attr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
+{
+    HAL_ASSERT(mode != APM_SEC_MODE_TEE);
+
+    switch (ctrl_mod) {
+        case APM_CTRL_HP_APM:
+            apm_ll_hp_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+            break;
+#if SOC_APM_LP_APM0_SUPPORTED
+        case APM_CTRL_LP_APM0:
+            apm_ll_lp_apm0_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+            break;
+#endif
+        case APM_CTRL_LP_APM:
+            apm_ll_lp_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+            break;
+#if SOC_APM_CPU_APM_SUPPORTED
+        case APM_CTRL_CPU_APM:
+            apm_ll_cpu_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+            break;
+#endif
+        default:
+            break;
+    }
+}
+
 void apm_hal_set_region_filter_cfg(apm_ctrl_module_t ctrl_mod, apm_security_mode_t mode, const apm_hal_ctrl_region_cfg_t *regn_cfg)
 {
     HAL_ASSERT(regn_cfg);
+    HAL_ASSERT(mode != APM_SEC_MODE_TEE);
 
     switch (ctrl_mod) {
         case APM_CTRL_HP_APM:

components/hal/esp32c61/include/hal/apm_ll.h

@@ -14,6 +14,8 @@
 #include "soc/hp_apm_struct.h"
 #include "soc/lp_apm_reg.h"
 #include "soc/lp_apm_struct.h"
+#include "soc/cpu_apm_reg.h"
+#include "soc/cpu_apm_struct.h"
 
 #include "soc/pcr_reg.h"
 #include "soc/interrupts.h"
@@ -448,6 +450,195 @@ static inline int apm_ll_lp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path)
     return ETS_LP_APM_M0_INTR_SOURCE;
 }
 
+/**
+ * @brief Enable/disable controller filter for specific path in CPU-APM
+ *
+ * @param path Access path
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path));
+    } else {
+        REG_CLR_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path));
+    }
+}
+
+/**
+ * @brief Enable/disable all controller filters in CPU-APM
+ *
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_ctrl_filter_all(bool enable)
+{
+    REG_WRITE(CPU_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0);
+}
+
+/**
+ * @brief Enable/disable region filter in CPU-APM
+ *
+ * @param regn_num Region number
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_region_filter(uint32_t regn_num, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num));
+    } else {
+        REG_CLR_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num));
+    }
+}
+
+/**
+ * @brief Set region start address in CPU-APM
+ *
+ * @param regn_num Region number
+ * @param addr Start address
+ */
+static inline void apm_ll_cpu_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr)
+{
+    REG_WRITE(CPU_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
+}
+
+/**
+ * @brief Set region end address in CPU-APM
+ *
+ * @param regn_num Region number
+ * @param addr End address
+ */
+static inline void apm_ll_cpu_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr)
+{
+    REG_WRITE(CPU_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr);
+}
+
+/**
+ * @brief Set security mode region attributes in CPU-APM
+ *
+ * @param regn_num Region number
+ * @param mode Security mode
+ * @param regn_pms Region PMS attributes
+ */
+static inline void apm_ll_cpu_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
+{
+    uint32_t reg = CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num;
+    uint32_t val = REG_READ(reg);
+    val &= ~APM_REGION_PMS_MASK(mode);
+    val |= APM_REGION_PMS_FIELD(mode, regn_pms);
+    REG_WRITE(reg, val);
+}
+
+/**
+ * @brief Lock security mode region attributes in CPU-APM
+ *
+ * @param regn_num Region number
+ */
+static inline void apm_ll_cpu_apm_lock_sec_mode_region_attr(uint32_t regn_num)
+{
+    REG_SET_BIT(CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT);
+}
+
+/**
+ * @brief Get exception data (regn, master, security mode) from CPU-APM
+ *
+ * @param path Access path
+ * @return Exception data
+ */
+static inline uint32_t apm_ll_cpu_apm_get_excp_data(apm_ctrl_access_path_t path)
+{
+    return REG_READ(CPU_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path);
+}
+
+/**
+ * @brief Get exception status from CPU-APM
+ *
+ * @param path Access path
+ * @return Exception type
+ */
+static inline uint32_t apm_ll_cpu_apm_get_excp_type(apm_ctrl_access_path_t path)
+{
+    return REG_READ(CPU_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path);
+}
+
+/**
+ * @brief Get exception address from CPU-APM
+ *
+ * @param path Access path
+ * @return Exception address
+ */
+static inline uint32_t apm_ll_cpu_apm_get_excp_addr(apm_ctrl_access_path_t path)
+{
+    return REG_READ(CPU_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path);
+}
+
+/**
+ * @brief Get exception information from CPU-APM
+ *
+ * @param path Access path
+ * @param info Pointer to store exception information
+ */
+static inline void apm_ll_cpu_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info)
+{
+    cpu_apm_m0_exception_info0_reg_t reg;
+    reg.val = apm_ll_cpu_apm_get_excp_data(path);
+    info->regn = reg.apm_m0_exception_region;
+    info->mode = reg.apm_m0_exception_mode;
+    info->id   = reg.apm_m0_exception_id;
+
+    info->type = apm_ll_cpu_apm_get_excp_type(path);
+    info->addr = apm_ll_cpu_apm_get_excp_addr(path);
+}
+
+/**
+ * @brief Clear controller exception status in CPU-APM
+ *
+ * @param path Access path
+ */
+static inline void apm_ll_cpu_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path)
+{
+    REG_SET_BIT(CPU_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT);
+}
+
+/**
+ * @brief Enable/disable controller interrupt in CPU-APM
+ *
+ * @param path Access path
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable)
+{
+    if (enable) {
+        REG_SET_BIT(CPU_APM_INT_EN_REG, BIT(path));
+    } else {
+        REG_CLR_BIT(CPU_APM_INT_EN_REG, BIT(path));
+    }
+}
+
+/**
+ * @brief Enable/disable controller clock gating in CPU-APM
+ *
+ * @param enable True to enable, false to disable
+ */
+static inline void apm_ll_cpu_apm_enable_ctrl_clk_gating(bool enable)
+{
+    if (enable) {
+        REG_CLR_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN);
+    } else {
+        REG_SET_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN);
+    }
+}
+
+/**
+ * @brief Get controller interrupt source number from CPU-APM
+ *
+ * @param path Access path
+ * @return Interrupt source number
+ */
+static inline int apm_ll_cpu_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path)
+{
+    return ETS_CPU_APM_M0_INTR_SOURCE + path;
+}
+
 /**
  * @brief Enable/disable APM reset event bypass
  *

components/hal/include/hal/apm_hal.h

@@ -253,6 +253,33 @@ void apm_hal_enable_ctrl_filter_all(bool enable);
  */
 void apm_hal_enable_region_filter(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, bool enable);
 
+/**
+ * @brief Set the start address for the given region
+ *
+ * @param ctrl_mod APM controller module
+ * @param regn_num Region number
+ * @param addr Address
+ */
+void apm_hal_set_region_start_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr);
+
+/**
+ * @brief Set the end address for the given region
+ *
+ * @param ctrl_mod APM controller module
+ * @param regn_num Region number
+ * @param addr Address
+ */
+void apm_hal_set_region_end_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr);
+
+/**
+ * @brief Set the permissions for the specified security mode for the given region
+ *
+ * @param ctrl_mod APM controller module
+ * @param regn_num Region number
+ * @param mode Security mode
+ */
+void apm_hal_set_sec_mode_region_attr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms);
+
 /**
  * @brief Set region filter configuration
  *

components/hal/test_apps/tee_apm/CMakeLists.txt

@@ -0,0 +1,15 @@
+#This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.16)
+
+# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
+set(COMPONENTS main)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+project(test_tee_apm)
+
+include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
+message(STATUS "Checking tee/apm registers are not read-write by half-word")
+check_register_rw_half_word(SOC_MODULES "*tee"       # tee, lp_tee
+                                        "*apm *apm0" # hp_apm, lp_apm, cpu_apm, lp_apm0
+                            HAL_MODULES "apm")