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Bruce297Bruce297
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Merge branch 'refactor/rng_ll_s3' into 'master'
refactor(rng): refactor to use hal/ll apis for S3 Closes IDF-12536 See merge request espressif/esp-idf!39585
2 parents f1df2f3 + 9a57629 commit 9ac4a34

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7 files changed

+160
-92
lines changed

7 files changed

+160
-92
lines changed

‎components/bootloader_support/src/bootloader_random_esp32c5.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,18 @@
1111
#include "esp_private/regi2c_ctrl.h"
1212
#include "soc/lpperi_reg.h"
1313

14-
#define I2C_SAR_ADC_INIT_CODE_VAL 2150
14+
#define I2C_SAR_ADC_INIT_CODE_VAL 2150
15+
#define ADC_RNG_CLKM_DIV_NUM 0
16+
#define ADC_RNG_CLKM_DIV_B 0
17+
#define ADC_RNG_CLKM_DIV_A 0
1518

1619
void bootloader_random_enable(void)
1720
{
1821
adc_ll_reset_register();
1922
adc_ll_enable_bus_clock(true);
2023
adc_ll_enable_func_clock(true);
2124
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
22-
adc_ll_digi_controller_clk_div(0, 0, 0);
25+
adc_ll_digi_controller_clk_div(ADC_RNG_CLKM_DIV_NUM, ADC_RNG_CLKM_DIV_B, ADC_RNG_CLKM_DIV_A);
2326

2427
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
2528
#ifndef BOOTLOADER_BUILD

‎components/bootloader_support/src/bootloader_random_esp32c6.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,18 @@
1010
#include "hal/adc_types.h"
1111
#include "esp_private/regi2c_ctrl.h"
1212

13-
#define I2C_SAR_ADC_INIT_CODE_VAL 2150
13+
#define I2C_SAR_ADC_INIT_CODE_VAL 2150
14+
#define ADC_RNG_CLKM_DIV_NUM 0
15+
#define ADC_RNG_CLKM_DIV_B 0
16+
#define ADC_RNG_CLKM_DIV_A 0
1417

1518
void bootloader_random_enable(void)
1619
{
1720
adc_ll_reset_register();
1821
adc_ll_enable_bus_clock(true);
1922
adc_ll_enable_func_clock(true);
2023
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
21-
adc_ll_digi_controller_clk_div(0, 0, 0);
24+
adc_ll_digi_controller_clk_div(ADC_RNG_CLKM_DIV_NUM, ADC_RNG_CLKM_DIV_B, ADC_RNG_CLKM_DIV_A);
2225

2326
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
2427
#ifndef BOOTLOADER_BUILD

‎components/bootloader_support/src/bootloader_random_esp32c61.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,18 @@
1010
#include "hal/adc_types.h"
1111
#include "esp_private/regi2c_ctrl.h"
1212

13-
#define I2C_SAR_ADC_INIT_CODE_VAL 2150
13+
#define I2C_SAR_ADC_INIT_CODE_VAL 2150
14+
#define ADC_RNG_CLKM_DIV_NUM 0
15+
#define ADC_RNG_CLKM_DIV_B 0
16+
#define ADC_RNG_CLKM_DIV_A 0
1417

1518
void bootloader_random_enable(void)
1619
{
1720
adc_ll_reset_register();
1821
adc_ll_enable_bus_clock(true);
1922
adc_ll_enable_func_clock(true);
2023
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
21-
adc_ll_digi_controller_clk_div(0, 0, 0);
24+
adc_ll_digi_controller_clk_div(ADC_RNG_CLKM_DIV_NUM, ADC_RNG_CLKM_DIV_B, ADC_RNG_CLKM_DIV_A);
2225

2326
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
2427
#ifndef BOOTLOADER_BUILD

‎components/bootloader_support/src/bootloader_random_esp32h2.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,18 @@
1010
#include "hal/adc_types.h"
1111
#include "esp_private/regi2c_ctrl.h"
1212

13-
#define I2C_SAR_ADC_INIT_CODE_VAL 2150
13+
#define I2C_SAR_ADC_INIT_CODE_VAL 2150
14+
#define ADC_RNG_CLKM_DIV_NUM 0
15+
#define ADC_RNG_CLKM_DIV_B 0
16+
#define ADC_RNG_CLKM_DIV_A 0
1417

1518
void bootloader_random_enable(void)
1619
{
1720
adc_ll_reset_register();
1821
adc_ll_enable_bus_clock(true);
1922
adc_ll_enable_func_clock(true);
2023
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
21-
adc_ll_digi_controller_clk_div(0, 0, 0);
24+
adc_ll_digi_controller_clk_div(ADC_RNG_CLKM_DIV_NUM, ADC_RNG_CLKM_DIV_B, ADC_RNG_CLKM_DIV_A);
2225

2326
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
2427
#ifndef BOOTLOADER_BUILD

‎components/bootloader_support/src/bootloader_random_esp32p4.c‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,15 +12,18 @@
1212
#include "esp_private/periph_ctrl.h"
1313
#include "esp_private/adc_share_hw_ctrl.h"
1414

15-
#define I2C_SAR_ADC_INIT_CODE_VAL 2166
15+
#define I2C_SAR_ADC_INIT_CODE_VAL 2166
16+
#define ADC_RNG_CLKM_DIV_NUM 0
17+
#define ADC_RNG_CLKM_DIV_B 0
18+
#define ADC_RNG_CLKM_DIV_A 0
1619

1720
void bootloader_random_enable(void)
1821
{
1922
_adc_ll_reset_register();
2023
_adc_ll_enable_bus_clock(true);
2124

2225
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
23-
adc_ll_digi_controller_clk_div(0, 0, 0);
26+
adc_ll_digi_controller_clk_div(ADC_RNG_CLKM_DIV_NUM, ADC_RNG_CLKM_DIV_B, ADC_RNG_CLKM_DIV_A);
2427

2528
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
2629
#ifndef BOOTLOADER_BUILD
@@ -69,4 +72,6 @@ void bootloader_random_disable(void)
6972
ANALOG_CLOCK_DISABLE();
7073
adc_ll_digi_controller_clk_div(4, 0, 0);
7174
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_XTAL);
75+
76+
adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
7277
}

‎components/bootloader_support/src/bootloader_random_esp32s3.c‎

Lines changed: 58 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,19 @@
11
/*
2-
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66
#include "sdkconfig.h"
77
#include "bootloader_random.h"
8-
#include "esp_log.h"
9-
#include "soc/system_reg.h"
108
#include "soc/syscon_reg.h"
11-
#include "soc/apb_saradc_reg.h"
12-
#include "soc/rtc_cntl_reg.h"
13-
#include "soc/sens_reg.h"
14-
#include "hal/regi2c_ctrl.h"
15-
#include "soc/regi2c_saradc.h"
9+
#include "esp_private/regi2c_ctrl.h"
10+
#include "hal/adc_ll.h"
11+
#include "hal/adc_types.h"
12+
#include "hal/regi2c_ctrl_ll.h"
13+
14+
#define ADC_RNG_CLKM_DIV_NUM 3
15+
#define ADC_RNG_CLKM_DIV_B 0
16+
#define ADC_RNG_CLKM_DIV_A 0
1617

1718
void bootloader_random_enable(void)
1819
{
@@ -22,81 +23,60 @@ void bootloader_random_enable(void)
2223
// but enabling the SAR ADC as well adds some insurance.)
2324
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
2425

25-
/// Enable SAR ADC to read a disconnected input for additional entropy
26-
27-
// Reset ADC clock
28-
SET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_APB_SARADC_CLK_EN);
29-
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_APB_SARADC_CLK_EN);
30-
31-
// Enable clock and select clock source for ADC digital controller
32-
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); //APB clock
33-
SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED);
34-
SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN);
35-
36-
// Read freq = apb_clk / (APB_SARADC_CLKM_DIV_NUM + 1) / TIMER_TARGET / 2
37-
// Internal ADC sample freq = apb_clk / (APB_SARADC_CLKM_DIV_NUM + 1) / (APB_SARADC_SAR_CLK_DIV + 1)
38-
// Read frequency has to be at least 35 times lower than the sampling frequency
39-
40-
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLKM_DIV_NUM, 3);
41-
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 3); // SAR clock divider has to be at least 2
42-
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 70);
43-
44-
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_START_FORCE);
45-
REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3);
46-
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT);
47-
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 1);
48-
49-
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR2_PATT_LEN, 0);
50-
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG,0xafffff); // Test internal voltage if the channel info is 0xa.
51-
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0);
52-
WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG,0xafffff); // Test internal voltage if the channel info is 0xa.
53-
54-
// Enable adc1 digital controller
55-
SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
56-
57-
// Set SARADC2 arbiter
58-
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_MUX_REG, SENS_SAR2_RTC_FORCE);
59-
CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE);
60-
CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_FIX_PRIORITY);
61-
62-
// Disable ADC filter
63-
REG_SET_FIELD(APB_SARADC_FILTER_CTRL0_REG, APB_SARADC_FILTER_CHANNEL0, 0xD);
64-
REG_SET_FIELD(APB_SARADC_FILTER_CTRL0_REG, APB_SARADC_FILTER_CHANNEL1, 0xD);
65-
66-
// Start ADC sample
67-
SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_SEL);
68-
SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
69-
70-
/*Choose the appropriate internal voltage to measure*/
71-
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 1);
72-
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1);
73-
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
74-
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
26+
_adc_ll_reset_register();
27+
_adc_ll_enable_bus_clock(true);
28+
_adc_ll_enable_bus_clock(false);
29+
30+
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_APB);
31+
adc_ll_digi_controller_clk_div(ADC_RNG_CLKM_DIV_NUM, ADC_RNG_CLKM_DIV_B, ADC_RNG_CLKM_DIV_A);
32+
33+
#ifndef BOOTLOADER_BUILD
34+
regi2c_saradc_enable();
35+
#else
36+
regi2c_ctrl_ll_i2c_sar_periph_enable();
37+
#endif
38+
// enable analog i2c master clock for RNG runtime
39+
ANALOG_CLOCK_ENABLE();
40+
41+
adc_ll_regi2c_init();
42+
43+
adc_digi_pattern_config_t pattern_config = {};
44+
pattern_config.unit = ADC_UNIT_1;
45+
pattern_config.atten = ADC_ATTEN_DB_12;
46+
pattern_config.channel = ADC_CHANNEL_10; //Use reserved channel to get internal voltage
47+
adc_ll_digi_set_pattern_table(ADC_UNIT_1, 0, pattern_config);
48+
pattern_config.unit = ADC_UNIT_2;
49+
pattern_config.atten = ADC_ATTEN_DB_12;
50+
pattern_config.channel = ADC_CHANNEL_10; //Use reserved ADC2 and reserved channel to get internal voltage
51+
adc_ll_digi_set_pattern_table(ADC_UNIT_2, 1, pattern_config);
52+
adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, 1);
53+
adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, 1);
54+
55+
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_BOTH_UNIT);
56+
57+
adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_DIG);
58+
adc_ll_disable_sleep_controller();
59+
adc_ll_set_arbiter_work_mode(ADC_ARB_MODE_LOOP);
60+
61+
adc_ll_digi_set_clk_div(3);
62+
adc_ll_digi_set_trigger_interval(70);
63+
adc_ll_digi_trigger_enable();
7564
}
7665

77-
//TODO: IDF-4714
7866
void bootloader_random_disable(void)
7967
{
80-
/* Restore internal I2C bus state */
81-
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 0);
82-
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
83-
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
84-
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
68+
adc_ll_digi_trigger_disable();
69+
adc_ll_digi_reset_pattern_table();
8570

86-
//Power off SAR ADC
87-
REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0);
88-
//return to ADC RTC controller
89-
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
90-
//Invalidate ADC digital trigger timer
91-
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
71+
adc_ll_regi2c_adc_deinit();
72+
#ifndef BOOTLOADER_BUILD
73+
regi2c_saradc_disable();
74+
#endif
9275

93-
//Disable ADC digital part
94-
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_APB_SARADC_CLK_EN);
95-
//Hold reset bit for ADC digital part
96-
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_APB_SARADC_RST);
76+
// disable analog i2c master clock
77+
ANALOG_CLOCK_DISABLE();
78+
adc_ll_digi_controller_clk_div(4, 0, 0);
79+
adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_APB);
9780

98-
/* Note: the 8M CLK entropy source continues running even after this function is called,
99-
but as mentioned above it's better to enable Wi-Fi or BT or call bootloader_random_enable()
100-
in order to get a secondary entropy source.
101-
*/
81+
adc_ll_set_controller(ADC_UNIT_1, ADC_LL_CTRL_ULP);
10282
}

‎components/hal/esp32s3/include/hal/adc_ll.h‎

Lines changed: 75 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -253,6 +253,17 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
253253
}
254254
}
255255

256+
/**
257+
* Rest pattern table to default value
258+
*/
259+
static inline void adc_ll_digi_reset_pattern_table(void)
260+
{
261+
for(int i = 0; i < 4; i++) {
262+
APB_SARADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
263+
APB_SARADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
264+
}
265+
}
266+
256267
/**
257268
* Set pattern table for digital controller.
258269
* The pattern table that defines the conversion rules for each SAR ADC. Each table has 12 items, in which channel selection,
@@ -619,28 +630,28 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
619630
* @brief Enable the ADC clock
620631
* @param enable true to enable, false to disable
621632
*/
622-
static inline void adc_ll_enable_bus_clock(bool enable)
633+
static inline void _adc_ll_enable_bus_clock(bool enable)
623634
{
624635
SYSTEM.perip_clk_en0.apb_saradc_clk_en = enable;
625636
}
626637
// SYSTEM.perip_clk_en0 is a shared register, so this function must be used in an atomic way
627638
#define adc_ll_enable_bus_clock(...) do { \
628639
(void)__DECLARE_RCC_ATOMIC_ENV; \
629-
adc_ll_enable_bus_clock(__VA_ARGS__); \
640+
_adc_ll_enable_bus_clock(__VA_ARGS__); \
630641
} while(0)
631642

632643
/**
633644
* @brief Reset ADC module
634645
*/
635-
static inline void adc_ll_reset_register(void)
646+
static inline void _adc_ll_reset_register(void)
636647
{
637648
SYSTEM.perip_rst_en0.apb_saradc_rst = 1;
638649
SYSTEM.perip_rst_en0.apb_saradc_rst = 0;
639650
}
640651
// SYSTEM.perip_rst_en0 is a shared register, so this function must be used in an atomic way
641652
#define adc_ll_reset_register(...) do { \
642653
(void)__DECLARE_RCC_ATOMIC_ENV; \
643-
adc_ll_reset_register(__VA_ARGS__); \
654+
_adc_ll_reset_register(__VA_ARGS__); \
644655
} while(0)
645656

646657
/**
@@ -888,6 +899,66 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
888899
}
889900
}
890901

902+
/**
903+
* Set the SAR DTEST param
904+
*
905+
* @param param DTEST value
906+
*/
907+
__attribute__((always_inline))
908+
static inline void adc_ll_set_dtest_param(uint32_t param)
909+
{
910+
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, param);
911+
}
912+
913+
/**
914+
* Set the SAR ENT param
915+
*
916+
* @param param ENT value
917+
*/
918+
__attribute__((always_inline))
919+
static inline void adc_ll_set_ent_param(uint32_t param)
920+
{
921+
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, param);
922+
}
923+
924+
/**
925+
* Enable/disable the calibration voltage reference for ADC unit.
926+
*
927+
* @param adc_n ADC index number.
928+
* @param en true to enable, false to disable
929+
*/
930+
__attribute__((always_inline))
931+
static inline void adc_ll_enable_calibration_ref(adc_unit_t adc_n, bool en)
932+
{
933+
(void)adc_n;
934+
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, en);
935+
}
936+
937+
/**
938+
* Init regi2c SARADC registers
939+
*/
940+
__attribute__((always_inline))
941+
static inline void adc_ll_regi2c_init(void)
942+
{
943+
adc_ll_set_dtest_param(0);
944+
adc_ll_set_ent_param(1);
945+
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
946+
adc_ll_enable_calibration_ref(ADC_UNIT_1, true);
947+
adc_ll_enable_calibration_ref(ADC_UNIT_2, true);
948+
}
949+
950+
/**
951+
* Deinit regi2c SARADC registers
952+
*/
953+
__attribute__((always_inline))
954+
static inline void adc_ll_regi2c_adc_deinit(void)
955+
{
956+
adc_ll_set_dtest_param(0);
957+
adc_ll_set_ent_param(0);
958+
adc_ll_enable_calibration_ref(ADC_UNIT_1, false);
959+
adc_ll_enable_calibration_ref(ADC_UNIT_2, false);
960+
}
961+
891962
/**
892963
* Output ADC internal reference voltage to channels, only available for ADC2 on ESP32.
893964
*

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