feat(psram): psram support on h4

Author: Icarus113

components/esp_common/test_apps/.build-test-rules.yml

@@ -4,3 +4,4 @@ components/esp_common/test_apps/esp_common:
   disable:
     - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
     - if: CONFIG_NAME == "psram_noinit" and SOC_SPIRAM_SUPPORTED != 1
+    - if: CONFIG_NAME == "xip_psram" and SOC_SPIRAM_XIP_SUPPORTED != 1

components/esp_common/test_apps/esp_common/pytest_esp_common.py

@@ -5,6 +5,7 @@
 import pytest
 from pytest_embedded import Dut
 from pytest_embedded_idf.utils import idf_parametrize
+from pytest_embedded_idf.utils import soc_filtered_targets
 
 
 @pytest.mark.generic
@@ -27,7 +28,7 @@ def test_esp_common(dut: Dut) -> None:
     ],
     indirect=True,
 )
-@idf_parametrize('target', ['esp32', 'esp32s2', 'esp32s3', 'esp32p4', 'esp32c5'], indirect=['target'])
+@idf_parametrize('target', soc_filtered_targets('SOC_SPIRAM_SUPPORTED == 1'), indirect=['target'])
 def test_esp_attr_psram_noinit(dut: Dut) -> None:
     dut.run_all_single_board_cases()
 
@@ -39,7 +40,7 @@ def test_esp_attr_psram_noinit(dut: Dut) -> None:
     ['psram_noinit'],
     indirect=True,
 )
-@idf_parametrize('target', ['supported_targets'], indirect=['target'])
+@idf_parametrize('target', soc_filtered_targets('SOC_SPIRAM_SUPPORTED == 1'), indirect=['target'])
 def test_esp_attr_psram_noinit_multiple_stages(case_tester: Any) -> None:
     case_tester.run_all_multi_stage_cases()
 
@@ -53,7 +54,7 @@ def test_esp_attr_psram_noinit_multiple_stages(case_tester: Any) -> None:
     ],
     indirect=True,
 )
-@idf_parametrize('target', ['esp32', 'esp32s2', 'esp32s3', 'esp32p4', 'esp32c5'], indirect=['target'])
+@idf_parametrize('target', soc_filtered_targets('SOC_SPIRAM_SUPPORTED == 1'), indirect=['target'])
 def test_esp_attr_psram(dut: Dut) -> None:
     dut.run_all_single_board_cases()
 
@@ -62,33 +63,9 @@ def test_esp_attr_psram(dut: Dut) -> None:
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
-    ['xip_psram_esp32s2'],
-    indirect=True,
-)
-@idf_parametrize('target', ['esp32s2'], indirect=['target'])
-def test_esp_attr_xip_psram_esp32s2(dut: Dut) -> None:
-    dut.run_all_single_board_cases()
-
-
-# psram attr tests with xip_psram
-@pytest.mark.generic
-@pytest.mark.parametrize(
-    'config',
-    ['xip_psram_esp32s3'],
-    indirect=True,
-)
-@idf_parametrize('target', ['esp32s3'], indirect=['target'])
-def test_esp_attr_xip_psram_esp32s3(dut: Dut) -> None:
-    dut.run_all_single_board_cases()
-
-
-# psram attr tests with xip_psram
-@pytest.mark.generic
-@pytest.mark.parametrize(
-    'config',
-    ['xip_psram_esp32p4'],
+    ['xip_psram'],
     indirect=True,
 )
-@idf_parametrize('target', ['esp32p4'], indirect=['target'])
-def test_esp_attr_xip_psram_esp32p4(dut: Dut) -> None:
+@idf_parametrize('target', soc_filtered_targets('SOC_SPIRAM_XIP_SUPPORTED == 1'), indirect=['target'])
+def test_esp_attr_xip_psram(dut: Dut) -> None:
     dut.run_all_single_board_cases()

components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4 renamed to components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram

@@ -1,6 +1,5 @@
 # For XiP PSRAM EXT_RAM_BSS_ATTR
 
-CONFIG_IDF_TARGET="esp32p4"
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_XIP_FROM_PSRAM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y

components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2

@@ -9,7 +9,6 @@
 #include "esp_log.h"
 #include "esp_private/esp_psram_impl.h"
 #include "rom/spi_flash.h"
-#include "rom/opi_flash.h"
 #include "esp_rom_gpio.h"
 #include "esp_rom_efuse.h"
 #include "hal/gpio_hal.h"
@@ -294,7 +293,8 @@ static void s_config_psram_clock(bool init_state)
     } else {
         // This function can be extended if we have other psram frequency
 
-#if (CONFIG_SPIRAM_SPEED == 80)
+#if (CONFIG_SPIRAM_SPEED == 80) || (CONFIG_SPIRAM_SPEED == 48)
+        // IDF-13632, update 48M to 64M
         clock_conf = psram_ctrlr_ll_calculate_clock_reg(1);
 #elif (CONFIG_SPIRAM_SPEED == 40)
         clock_conf = psram_ctrlr_ll_calculate_clock_reg(2);

components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3

@@ -0,0 +1,78 @@
+config SPIRAM
+    bool "Support for external, SPI-connected RAM"
+    default "n"
+    help
+        This enables support for an external SPI RAM chip, connected in parallel with the
+        main SPI flash chip.
+
+menu "SPI RAM config"
+    depends on SPIRAM
+
+    choice SPIRAM_MODE
+        prompt "Mode of SPI RAM chip in use"
+        default SPIRAM_MODE_QUAD
+
+        config SPIRAM_MODE_QUAD
+            bool "Quad Mode PSRAM"
+
+    endchoice
+
+    choice SPIRAM_SPEED
+        prompt "Set RAM clock speed"
+        default SPIRAM_SPEED_48M
+        help
+            Select the speed for the SPI RAM chip.
+
+        config SPIRAM_SPEED_48M
+            bool "48Mhz clock speed"
+    endchoice
+
+    config SPIRAM_SPEED
+        int
+        default 48 if SPIRAM_SPEED_48M
+        default 64 if SPIRAM_SPEED_64M
+
+    config SPIRAM_FETCH_INSTRUCTIONS
+        bool
+        help
+            Enable this option allows moving application's instruction segment from the SPI Flash to PSRAM
+
+    config SPIRAM_RODATA
+        bool
+        help
+            Enable this option allows moving application's rodata segment from the SPI Flash to
+            PSRAM
+
+    config SPIRAM_XIP_FROM_PSRAM
+        bool "Enable Executable in place from (XiP) from PSRAM feature (READ HELP)"
+        default n
+        select SPIRAM_FETCH_INSTRUCTIONS
+        select SPIRAM_RODATA
+        select SPIRAM_FLASH_LOAD_TO_PSRAM
+        help
+            If enabled, firmware in flash including instructions and data will be moved into PSRAM on startup,
+            firmware code will execute directly from PSRAM.
+
+            With this option enabled, code that requires execution during an MSPI1 Flash operation
+            does not have to be placed in IRAM. Therefore codes that need to be executing during Flash
+            operations can continue working normally.
+
+            This feature is useful for high throughput peripheral involved applications to improve
+            the performance during MSPI1 flash operations.
+
+    config SPIRAM_FLASH_LOAD_TO_PSRAM
+        bool
+        help
+            This is a helper indicating this condition:
+            `CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_IDF_TARGET_ESP32H4`
+
+    config SPIRAM_ECC_ENABLE
+        bool "Enable PSRAM ECC"
+        default n
+        help
+            Enable MSPI Error-Correcting Code function when accessing PSRAM.
+
+            If enabled, 1/8 of the PSRAM total size will be reserved for error-correcting code.
+
+    source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common"    # insert non-chip-specific items here
+endmenu

components/esp_psram/device/esp_psram_impl_ap_quad.c

@@ -1,4 +1,4 @@
-| Supported Targets | ESP32 | ESP32-C5 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C5 | ESP32-C61 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 This test app is used to test PSRAM

components/esp_psram/esp32h4/Kconfig.spiram

@@ -455,6 +455,124 @@ uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
 
 extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
 
+typedef struct {
+    uint16_t cmd;                /*!< Command value */
+    uint16_t cmdBitLen;          /*!< Command byte length*/
+    uint32_t *addr;              /*!< Point to address value*/
+    uint32_t addrBitLen;         /*!< Address byte length*/
+    uint32_t *txData;            /*!< Point to send data buffer*/
+    uint32_t txDataBitLen;       /*!< Send data byte length.*/
+    uint32_t *rxData;            /*!< Point to receive data buffer*/
+    uint32_t rxDataBitLen;       /*!< Receive Data byte length.*/
+    uint32_t dummyBitLen;
+} esp_rom_spi_cmd_t;
+
+// Definition of MX25UM25645G Octa Flash
+// SPI status register
+#define ESP_ROM_SPIFLASH_BUSY_FLAG     BIT0
+#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
+#define ESP_ROM_SPIFLASH_BP0           BIT2
+#define ESP_ROM_SPIFLASH_BP1           BIT3
+#define ESP_ROM_SPIFLASH_BP2           BIT4
+#define ESP_ROM_SPIFLASH_WR_PROTECT    (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
+#define ESP_ROM_SPIFLASH_QE            BIT9
+
+#define FLASH_OP_MODE_RDCMD_DOUT       0x3B
+#define ESP_ROM_FLASH_SECTOR_SIZE      0x1000
+#define ESP_ROM_FLASH_BLOCK_SIZE_64K   0x10000
+#define ESP_ROM_FLASH_PAGE_SIZE        256
+
+// FLASH commands
+#define ROM_FLASH_CMD_RDID             0x9F
+#define ROM_FLASH_CMD_WRSR             0x01
+#define ROM_FLASH_CMD_WRSR2            0x31 /* Not all SPI flash uses this command */
+#define ROM_FLASH_CMD_WREN             0x06
+#define ROM_FLASH_CMD_WRDI             0x04
+#define ROM_FLASH_CMD_RDSR             0x05
+#define ROM_FLASH_CMD_RDSR2            0x35 /* Not all SPI flash uses this command */
+#define ROM_FLASH_CMD_ERASE_SEC        0x20
+#define ROM_FLASH_CMD_ERASE_BLK_32K    0x52
+#define ROM_FLASH_CMD_ERASE_BLK_64K    0xD8
+#define ROM_FLASH_CMD_OTPEN            0x3A /* Enable OTP mode, not all SPI flash uses this command */
+#define ROM_FLASH_CMD_RSTEN            0x66
+#define ROM_FLASH_CMD_RST              0x99
+
+#define ROM_FLASH_CMD_SE4B             0x21
+#define ROM_FLASH_CMD_SE4B_OCT         0xDE21
+#define ROM_FLASH_CMD_BE4B             0xDC
+#define ROM_FLASH_CMD_BE4B_OCT         0x23DC
+#define ROM_FLASH_CMD_RSTEN_OCT        0x9966
+#define ROM_FLASH_CMD_RST_OCT          0x6699
+
+#define ROM_FLASH_CMD_FSTRD4B_STR      0x13EC
+#define ROM_FLASH_CMD_FSTRD4B_DTR      0x11EE
+#define ROM_FLASH_CMD_FSTRD4B          0x0C
+#define ROM_FLASH_CMD_PP4B             0x12
+#define ROM_FLASH_CMD_PP4B_OCT         0xED12
+
+#define ROM_FLASH_CMD_RDID_OCT         0x609F
+#define ROM_FLASH_CMD_WREN_OCT         0xF906
+#define ROM_FLASH_CMD_RDSR_OCT         0xFA05
+#define ROM_FLASH_CMD_RDCR2            0x71
+#define ROM_FLASH_CMD_RDCR2_OCT        0x8E71
+#define ROM_FLASH_CMD_WRCR2            0x72
+#define ROM_FLASH_CMD_WRCR2_OCT        0x8D72
+
+// Definitions for GigaDevice GD25LX256E Flash
+#define ROM_FLASH_CMD_RDFSR_GD            0x70
+#define ROM_FLASH_CMD_RD_GD               0x03
+#define ROM_FLASH_CMD_RD4B_GD             0x13
+#define ROM_FLASH_CMD_FSTRD_GD            0x0B
+#define ROM_FLASH_CMD_FSTRD4B_GD          0x0C
+#define ROM_FLASH_CMD_FSTRD_OOUT_GD       0x8B
+#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD     0x7C
+#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD     0xCB
+#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD   0xCC
+#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD   0xFD
+
+#define ROM_FLASH_CMD_PP_GD               0x02
+#define ROM_FLASH_CMD_PP4B_GD             0x12
+#define ROM_FLASH_CMD_PP_OOUT_GD          0x82
+#define ROM_FLASH_CMD_PP4B_OOUT_GD        0x84
+#define ROM_FLASH_CMD_PP_OIO_GD           0xC2
+#define ROM_FLASH_CMD_PP4B_OIOSTR_GD      0x8E
+
+#define ROM_FLASH_CMD_SE_GD               0x20
+#define ROM_FLASH_CMD_SE4B_GD             0x21
+#define ROM_FLASH_CMD_BE32K_GD            0x52
+#define ROM_FLASH_CMD_BE32K4B_GD          0x5C
+#define ROM_FLASH_CMD_BE64K_GD            0xD8
+#define ROM_FLASH_CMD_BE64K4B_GD          0xDC
+
+#define ROM_FLASH_CMD_EN4B_GD             0xB7
+#define ROM_FLASH_CMD_DIS4B_GD            0xE9
+
+// spi user mode command config
+/**
+ * @brief Config the spi user command
+ * @param spi_num spi port
+ * @param pcmd pointer to accept the spi command struct
+ */
+void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd);
+
+/**
+ * @brief Start a spi user command sequence
+ * @param spi_num spi port
+ * @param rx_buf buffer pointer to receive data
+ * @param rx_len receive data length in byte
+ * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
+ * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
+ */
+void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
+
+// set SPI read/write mode
+/**
+ * @brief Set SPI operation mode
+ * @param spi_num spi port
+ * @param mode Flash Read Mode
+ */
+void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_psram/test_apps/psram/README.md

@@ -64,6 +64,11 @@ MEMORY
   /* (See irom_seg for meaning of 0x20 offset in the above.) */
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 
+  /**
+   * `extern_ram_seg` and `drom_seg` / `irom_seg` share the same bus and the address region.
+   * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
+   */
+  extern_ram_seg(RWX) :        org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
 }
 
 /* Heap ends at top of sram_seg */