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songruosongruo
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feat(regi2c): add regi2c support for esp32h21
1 parent 79d503f commit 9ef152c

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21 files changed

+370
-325
lines changed

21 files changed

+370
-325
lines changed

‎components/bootloader_support/src/esp32c5/bootloader_esp32c5.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,6 @@ static void bootloader_super_wdt_auto_feed(void)
8686
static inline void bootloader_hardware_init(void)
8787
{
8888
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
89-
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
9089
regi2c_ctrl_ll_master_configure_clock();
9190
}
9291

‎components/bootloader_support/src/esp32c61/bootloader_esp32c61.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,6 @@ static void bootloader_super_wdt_auto_feed(void)
8787
static inline void bootloader_hardware_init(void)
8888
{
8989
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
90-
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
9190
regi2c_ctrl_ll_master_configure_clock();
9291
}
9392

‎components/bootloader_support/src/esp32h21/bootloader_esp32h21.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -89,8 +89,8 @@ static inline void bootloader_hardware_init(void)
8989
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
9090
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
9191

92-
//TODO: [ESP32H21] IDF-11550, regi2c atomic clock
93-
regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
92+
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
93+
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-11548 Remove this?
9494
regi2c_ctrl_ll_master_configure_clock();
9595
}
9696

‎components/esp_rom/patches/esp_rom_regi2c_esp32h21.c‎

Lines changed: 44 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/**
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -8,73 +8,16 @@
88
#include "soc/i2c_ana_mst_reg.h"
99
#include "hal/regi2c_ctrl_ll.h"
1010

11-
/**
12-
* BB - 0x67 - BIT0
13-
* TXRF - 0x6B - BIT1
14-
* SDM - 0x63 - BIT2
15-
* PLL - 0x62 - BIT3
16-
* BIAS - 0x6A - BIT4
17-
* BBPLL - 0x66 - BIT5
18-
* ULP - 0x61 - BIT6
19-
* SAR - 0x69 - BIT7
20-
* PMU - 0x6d - BIT8
21-
*/
22-
23-
#define REGI2C_BIAS_MST_SEL (BIT(8))
24-
#define REGI2C_BBPLL_MST_SEL (BIT(9))
25-
#define REGI2C_ULP_CAL_MST_SEL (BIT(10))
26-
#define REGI2C_SAR_I2C_MST_SEL (BIT(11))
27-
#define REGI2C_DIG_REG_MST_SEL (BIT(12))
28-
29-
#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_MST_ANA_CONF1_M)
30-
#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_MST_ANA_CONF1_M)
31-
#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_MST_ANA_CONF1_M)
32-
#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_MST_ANA_CONF1_M)
33-
#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_MST_ANA_CONF1_M)
34-
35-
#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
36-
37-
#define REGI2C_RTC_BUSY (BIT(25))
38-
#define REGI2C_RTC_BUSY_M (BIT(25))
39-
#define REGI2C_RTC_BUSY_V 0x1
40-
#define REGI2C_RTC_BUSY_S 25
41-
42-
#define REGI2C_RTC_WR_CNTL (BIT(24))
43-
#define REGI2C_RTC_WR_CNTL_M (BIT(24))
44-
#define REGI2C_RTC_WR_CNTL_V 0x1
45-
#define REGI2C_RTC_WR_CNTL_S 24
46-
47-
#define REGI2C_RTC_DATA 0x000000FF
48-
#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
49-
#define REGI2C_RTC_DATA_V 0xFF
50-
#define REGI2C_RTC_DATA_S 16
51-
52-
#define REGI2C_RTC_ADDR 0x000000FF
53-
#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
54-
#define REGI2C_RTC_ADDR_V 0xFF
55-
#define REGI2C_RTC_ADDR_S 8
56-
57-
#define REGI2C_RTC_SLAVE_ID 0x000000FF
58-
#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
59-
#define REGI2C_RTC_SLAVE_ID_V 0xFF
60-
#define REGI2C_RTC_SLAVE_ID_S 0
61-
6211
/* SLAVE */
63-
64-
#define REGI2C_BBPLL (0x66)
65-
#define REGI2C_BBPLL_HOSTID 0
66-
67-
#define REGI2C_BIAS (0x6a)
68-
#define REGI2C_BIAS_HOSTID 0
69-
70-
#define REGI2C_PMU (0x6d)
71-
#define REGI2C_PMU_HOSTID 0
72-
73-
#define REGI2C_ULP_CAL (0x61)
74-
#define REGI2C_ULP_CAL_HOSTID 0
75-
76-
#define REGI2C_SAR_I2C (0x69)
77-
#define REGI2C_SAR_I2C_HOSTID 0
12+
#define REGI2C_BBPLL 0x66 // regi2c_bbpll.h
13+
#define REGI2C_BBTOP 0x67
14+
#define REGI2C_DCDC 0x6D // regi2c_pmu.h
15+
#define REGI2C_PERIF 0x69 // regi2c_saradc.h
16+
#define REGI2C_RFPLL 0x62
17+
#define REGI2C_SDM 0x63
18+
#define REGI2C_TXTOP 0x6B
19+
#define REGI2C_ULP 0x61 // regi2c_lp_bias.h
20+
#define REGI2C_BIAS 0x6A // regi2c_bias.h
7821

7922
/* SLAVE END */
8023

@@ -86,33 +29,44 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
8629
static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
8730
{
8831
uint32_t i2c_sel = 0;
89-
regi2c_ctrl_ll_master_enable_clock(true);
32+
assert(regi2c_ctrl_ll_master_is_clock_enabled());
9033

9134
/* Before config I2C register, enable corresponding slave. */
9235
switch (block) {
93-
case REGI2C_BBPLL :
94-
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL);
95-
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK);
96-
break;
97-
case REGI2C_BIAS :
98-
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
99-
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK);
100-
break;
101-
case REGI2C_PMU:
102-
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
103-
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK);
104-
break;
105-
case REGI2C_ULP_CAL:
106-
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL);
107-
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK);
108-
break;
109-
case REGI2C_SAR_I2C:
110-
i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
111-
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK);
112-
break;
36+
case REGI2C_BBPLL:
37+
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBPLL_SEL);
38+
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBPLL_SEL & I2C_ANA_MST_ANA_CONF1_M);
39+
break;
40+
case REGI2C_BBTOP:
41+
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBTOP_SEL);
42+
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBTOP_SEL & I2C_ANA_MST_ANA_CONF1_M);
43+
break;
44+
case REGI2C_DCDC:
45+
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PMU_SEL);
46+
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PMU_SEL & I2C_ANA_MST_ANA_CONF1_M);
47+
break;
48+
case REGI2C_PERIF:
49+
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PERIF_SEL);
50+
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PERIF_SEL & I2C_ANA_MST_ANA_CONF1_M);
51+
break;
52+
case REGI2C_RFPLL:
53+
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PLL_SEL);
54+
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PLL_SEL & I2C_ANA_MST_ANA_CONF1_M);
55+
break;
56+
case REGI2C_SDM:
57+
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_SDM_SEL);
58+
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_SDM_SEL & I2C_ANA_MST_ANA_CONF1_M);
59+
break;
60+
case REGI2C_TXTOP:
61+
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_TXTOP_SEL);
62+
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_TXTOP_SEL & I2C_ANA_MST_ANA_CONF1_M);
63+
break;
64+
case REGI2C_ULP:
65+
i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_ULP_SEL);
66+
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_ULP_SEL & I2C_ANA_MST_ANA_CONF1_M);
67+
break;
11368
}
114-
115-
return (uint8_t)(i2c_sel ? 0: 1);
69+
return (uint8_t)(i2c_sel ? 0 : 1);
11670
}
11771

11872
uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)

‎components/hal/esp32/include/hal/regi2c_ctrl_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
5050
}
5151

5252
/**
53-
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
53+
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
5454
*/
5555
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
5656
{

‎components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
6969
}
7070

7171
/**
72-
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
72+
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
7373
*/
7474
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
7575
{

‎components/hal/esp32c3/include/hal/regi2c_ctrl_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
4949
}
5050

5151
/**
52-
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
52+
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
5353
*/
5454
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
5555
{

‎components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
110110
}
111111

112112
/**
113-
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
113+
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
114114
*/
115115
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
116116
{

‎components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
108108
}
109109

110110
/**
111-
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
111+
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
112112
*/
113113
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
114114
{

‎components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
110110
}
111111

112112
/**
113-
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
113+
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
114114
*/
115115
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
116116
{

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