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author
Jiang Jiang Jian
committed
Merge branch 'bugfix/clic_register_issues' into 'master'
fix(soc): fix clic register definition and description See merge request espressif/esp-idf!35538
2 parents 7947246 + 3f51e84 commit a509144

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‎components/soc/esp32c5/include/soc/clic_reg.h‎

Lines changed: 107 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -12,97 +12,159 @@ extern "C" {
1212

1313
#define NLBITS 3
1414
#define CLIC_EXT_INTR_NUM_OFFSET 16
15-
#define DUALCORE_CLIC_CTRL_OFF 0x10000
1615

17-
#define DR_REG_CLIC_BASE ( 0x20800000 )
18-
#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 )
16+
#define DR_REG_CLIC_BASE (0x20800000)
17+
#define DR_REG_CLIC_CTRL_BASE (0x20801000)
1918

2019
#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0)
21-
/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
22-
/*description: .*/
20+
/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[27:24] ;default: 4'd0 ; */
21+
/*description: user mode interrupt priority effective digits, the maximum value is 8..*/
22+
#define CLIC_INT_CONFIG_UNLBITS 0x0000000F
23+
#define CLIC_INT_CONFIG_UNLBITS_M ((CLIC_INT_CONFIG_UNLBITS_V) << (CLIC_INT_CONFIG_UNLBITS_S))
24+
#define CLIC_INT_CONFIG_UNLBITS_V 0xF
25+
#define CLIC_INT_CONFIG_UNLBITS_S 24
26+
/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[19:16] ;default: 4'd0 ; */
27+
/*description: supervisor mode interrupt priority effective digits, the maximum value is 8..*/
28+
#define CLIC_INT_CONFIG_SNLBITS 0x0000000F
29+
#define CLIC_INT_CONFIG_SNLBITS_M ((CLIC_INT_CONFIG_SNLBITS_V) << (CLIC_INT_CONFIG_SNLBITS_S))
30+
#define CLIC_INT_CONFIG_SNLBITS_V 0xF
31+
#define CLIC_INT_CONFIG_SNLBITS_S 16
32+
/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
33+
/*description: the effective number of bits in the privileged state.*/
2334
#define CLIC_INT_CONFIG_NMBITS 0x00000003
24-
#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S))
35+
#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V) << (CLIC_INT_CONFIG_NMBITS_S))
2536
#define CLIC_INT_CONFIG_NMBITS_V 0x3
26-
#define CLIC_INT_CONFIG_NMBITS_S 5
27-
/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
28-
/*description: .*/
29-
#define CLIC_INT_CONFIG_NLBITS 0x0000000F
30-
#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S))
31-
#define CLIC_INT_CONFIG_NLBITS_V 0xF
32-
#define CLIC_INT_CONFIG_NLBITS_S 1
33-
/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
34-
/*description: .*/
35-
#define CLIC_INT_CONFIG_NVBITS (BIT(0))
36-
#define CLIC_INT_CONFIG_NVBITS_M (BIT(0))
37-
#define CLIC_INT_CONFIG_NVBITS_V 0x1
38-
#define CLIC_INT_CONFIG_NVBITS_S 0
37+
#define CLIC_INT_CONFIG_NMBITS_S 4
38+
/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
39+
/*description: machine mode interrupt priority effective digits, the maximum value is 8.*/
40+
#define CLIC_INT_CONFIG_MNLBITS 0x0000000F
41+
#define CLIC_INT_CONFIG_MNLBITS_M ((CLIC_INT_CONFIG_MNLBITS_V) << (CLIC_INT_CONFIG_MNLBITS_S))
42+
#define CLIC_INT_CONFIG_MNLBITS_V 0xF
43+
#define CLIC_INT_CONFIG_MNLBITS_S 0
3944

4045
#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4)
41-
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
42-
/*description: .*/
46+
/* CLIC_INT_INFO_NUM_INT : RO ;bitpos:[24:21] ;default: 4'd3 ; */
47+
/*description: The effective bits of priority in the CLICINTCTL register.*/
4348
#define CLIC_INT_INFO_CTLBITS 0x0000000F
44-
#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S))
49+
#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V) << (CLIC_INT_INFO_CTLBITS_S))
4550
#define CLIC_INT_INFO_CTLBITS_V 0xF
4651
#define CLIC_INT_INFO_CTLBITS_S 21
47-
/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
48-
/*description: .*/
52+
/* CLIC_INT_INFO_VERSION : RO ;bitpos:[20:13] ;default: 8'd0 ; */
53+
/*description: The lower 4 bits are the modified version of the hardware implementation; the upper 4 bits are the CLIC
54+
architecture version information.*/
4955
#define CLIC_INT_INFO_VERSION 0x000000FF
50-
#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S))
56+
#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V) << (CLIC_INT_INFO_VERSION_S))
5157
#define CLIC_INT_INFO_VERSION_V 0xFF
5258
#define CLIC_INT_INFO_VERSION_S 13
53-
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
54-
/*description: .*/
55-
#define CLIC_INT_INFO_NUM_INT 0x00001FFF
56-
#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S))
57-
#define CLIC_INT_INFO_NUM_INT_V 0x1FFF
58-
#define CLIC_INT_INFO_NUM_INT_S 0
59+
/* CLIC_INT_INFO_NUM_INT : RO ;bitpos:[12:0] ;default: 13'd48 ; */
60+
/*description: number of interrupt sources.*/
61+
#define CLIC_INT_INFO_NUM_INT 0x00001FFF
62+
#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V) << (CLIC_INT_INFO_NUM_INT_S))
63+
#define CLIC_INT_INFO_NUM_INT_V 0x1FFF
64+
#define CLIC_INT_INFO_NUM_INT_S 0
5965

6066
#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8)
6167
/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
62-
/*description: .*/
63-
#define CLIC_CPU_INT_THRESH 0x000000FF
64-
#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S))
68+
/*description: Threshold for machine mode interruption..*/
69+
#define CLIC_CPU_INT_THRESH 0x000000FF
70+
#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V) << (CLIC_CPU_INT_THRESH_S))
6571
#define CLIC_CPU_INT_THRESH_V 0xFF
6672
#define CLIC_CPU_INT_THRESH_S 24
6773

68-
#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4)
69-
/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
70-
/*description: .*/
74+
#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i)*4)
75+
/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'h1f ; */
76+
/*description: This register is used to indicate the priority of each interrupt
77+
source participating in the arbitration, and at the same time to cooperate with
78+
CLICCFG.nlbits to generate the interrupt priority to the CPU.*/
7179
#define CLIC_INT_CTL 0x000000FF
72-
#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S))
80+
#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V) << (CLIC_INT_CTL_S))
7381
#define CLIC_INT_CTL_V 0xFF
7482
#define CLIC_INT_CTL_S 24
7583
/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
76-
/*description: .*/
84+
/*description: This field is used to configure the privileged mode of the interrupt.
85+
0: user mode, 3: machine mode*/
7786
#define CLIC_INT_ATTR_MODE 0x00000003
78-
#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S))
87+
#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V) << (CLIC_INT_ATTR_MODE_S))
7988
#define CLIC_INT_ATTR_MODE_V 0x3
8089
#define CLIC_INT_ATTR_MODE_S 22
8190
/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
82-
/*description: .*/
91+
/*description: This field is used to distinguish pulse interruption and level
92+
interruption. When trig[0] is 0, it means level interruption. When trig[0] is 1,
93+
trig[1] is 0, it means interrupt on rising edge, and trig[1] is 1 means interrupt
94+
on falling edge.*/
8395
#define CLIC_INT_ATTR_TRIG 0x00000003
84-
#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S))
96+
#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V) << (CLIC_INT_ATTR_TRIG_S))
8597
#define CLIC_INT_ATTR_TRIG_V 0x3
8698
#define CLIC_INT_ATTR_TRIG_S 17
8799
/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
88-
/*description: .*/
100+
/*description: Represents whether the interrupt is a hardware vector interrupt.*/
89101
#define CLIC_INT_ATTR_SHV (BIT(16))
90102
#define CLIC_INT_ATTR_SHV_M (BIT(16))
91103
#define CLIC_INT_ATTR_SHV_V 0x1
92104
#define CLIC_INT_ATTR_SHV_S 16
93105
/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
94-
/*description: .*/
106+
/*description: Interrupt Enable Register.*/
95107
#define CLIC_INT_IE (BIT(8))
96108
#define CLIC_INT_IE_M (BIT(8))
97109
#define CLIC_INT_IE_V 0x1
98110
#define CLIC_INT_IE_S 8
99111
/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
100-
/*description: .*/
112+
/*description: Interrupt Pending Register. This bit has different set and clear logic in the
113+
case of level interrupt and edge interrupt*/
101114
#define CLIC_INT_IP (BIT(0))
102115
#define CLIC_INT_IP_M (BIT(0))
103116
#define CLIC_INT_IP_V 0x1
104117
#define CLIC_INT_IP_S 0
105118

119+
// each of following registers are 8bits
120+
#define BYTE_CLIC_INT_IP_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4)
121+
/* BYTE_CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
122+
/*description: Interrupt Pending Register. This bit has different set and clear logic in the
123+
case of level interrupt and edge interrupt*/
124+
#define BYTE_CLIC_INT_IP (BIT(0))
125+
#define BYTE_CLIC_INT_IP_M (BIT(0))
126+
#define BYTE_CLIC_INT_IP_V 0x1
127+
#define BYTE_CLIC_INT_IP_S 0
128+
129+
#define BYTE_CLIC_INT_IE_REG(i) (DR_REG_CLIC_CTRL_BASE + 1 + (i) * 4)
130+
/* BYTE_CLIC_INT_IE : R/W ;bitpos:[0] ;default: 1'd0 ; */
131+
/*description: Interrupt Enable Register.*/
132+
#define BYTE_CLIC_INT_IE (BIT(0))
133+
#define BYTE_CLIC_INT_IE_M (BIT(0))
134+
#define BYTE_CLIC_INT_IE_V 0x1
135+
#define BYTE_CLIC_INT_IE_S 0
136+
137+
#define BYTE_CLIC_INT_ATTR_REG(i) (DR_REG_CLIC_CTRL_BASE + 2 + (i) * 4)
138+
/* BYTE_CLIC_INT_ATTR_SHV : R/W ;bitpos:[0] ;default: 1'd0 ; */
139+
/*description: 1 means hardware vector interrupt.*/
140+
#define BYTE_CLIC_INT_ATTR_SHV (BIT(0))
141+
#define BYTE_CLIC_INT_ATTR_SHV_M (BIT(0))
142+
#define BYTE_CLIC_INT_ATTR_SHV_V 0x1
143+
#define BYTE_CLIC_INT_ATTR_SHV_S 0
144+
/* BYTE_CLIC_INT_ATTR_TRIG: R/W ; bitpos:[2:1] ;default: 2'd0 ; */
145+
/*description:
146+
[X0] -> level trigger
147+
[01] -> rising edge trigger
148+
[11] -> falling edge trigger */
149+
#define BYTE_CLIC_INT_ATTR_TRIG 0x00000003
150+
#define BYTE_CLIC_INT_ATTR_TRIG_M ((BYTE_CLIC_INT_ATTR_TRIG_V) << (BYTE_CLIC_INT_ATTR_TRIG_S))
151+
#define BYTE_CLIC_INT_ATTR_TRIG_V 0x3
152+
#define BYTE_CLIC_INT_ATTR_TRIG_S 1
153+
/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:6] ;default: 2'd0 ; */
154+
/*description: privilege level for interrupt, 0: user mode, 3: machine mode */
155+
#define BYTE_CLIC_INT_ATTR_MODE 0x00000003
156+
#define BYTE_CLIC_INT_ATTR_MODE_M ((BYTE_CLIC_INT_ATTR_MODE_V) << (BYTE_CLIC_INT_ATTR_MODE_S))
157+
#define BYTE_CLIC_INT_ATTR_MODE_V 0x3
158+
#define BYTE_CLIC_INT_ATTR_MODE_S 6
159+
160+
#define BYTE_CLIC_INT_CTL_REG(i) (DR_REG_CLIC_CTRL_BASE + 3 + (i) * 4)
161+
/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:5] ;default: 3'd0 ; */
162+
/*description: interrupt priority */
163+
#define BYTE_CLIC_INT_CTL 0x00000007
164+
#define BYTE_CLIC_INT_CTL_M ((BYTE_CLIC_INT_CTL_V) << (BYTE_CLIC_INT_CTL_S))
165+
#define BYTE_CLIC_INT_CTL_V 0x7
166+
#define BYTE_CLIC_INT_CTL_S 5
167+
106168
#ifdef __cplusplus
107169
}
108170
#endif

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