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| 1 | +/* |
| 2 | + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | +#pragma once |
| 7 | + |
| 8 | +#include <stdbool.h> |
| 9 | +#include "soc/hwcrypto_reg.h" |
| 10 | +#include "soc/pcr_struct.h" |
| 11 | +#include "hal/sha_types.h" |
| 12 | + |
| 13 | +#ifdef __cplusplus |
| 14 | +extern "C" { |
| 15 | +#endif |
| 16 | + |
| 17 | + |
| 18 | +/** |
| 19 | + * @brief Enable the bus clock for SHA peripheral module |
| 20 | + * |
| 21 | + * @param enable true to enable the module, false to disable the module |
| 22 | + */ |
| 23 | +static inline void sha_ll_enable_bus_clock(bool enable) |
| 24 | +{ |
| 25 | + PCR.sha_conf.sha_clk_en = enable; |
| 26 | +} |
| 27 | + |
| 28 | +/** |
| 29 | + * @brief Reset the SHA peripheral module |
| 30 | + */ |
| 31 | +static inline void sha_ll_reset_register(void) |
| 32 | +{ |
| 33 | + PCR.sha_conf.sha_rst_en = 1; |
| 34 | + PCR.sha_conf.sha_rst_en = 0; |
| 35 | + |
| 36 | + // Clear reset on digital signature, hmac and ecdsa also, otherwise SHA is held in reset |
| 37 | + PCR.ds_conf.ds_rst_en = 0; |
| 38 | + PCR.hmac_conf.hmac_rst_en = 0; |
| 39 | + PCR.ecdsa_conf.ecdsa_rst_en = 0; |
| 40 | +} |
| 41 | + |
| 42 | +/** |
| 43 | + * @brief Start a new SHA block conversions (no initial hash in HW) |
| 44 | + * |
| 45 | + * @param sha_type The SHA algorithm type |
| 46 | + */ |
| 47 | +static inline void sha_ll_start_block(esp_sha_type sha_type) |
| 48 | +{ |
| 49 | + REG_WRITE(SHA_MODE_REG, sha_type); |
| 50 | + REG_WRITE(SHA_START_REG, 1); |
| 51 | +} |
| 52 | + |
| 53 | +/** |
| 54 | + * @brief Continue a SHA block conversion (initial hash in HW) |
| 55 | + * |
| 56 | + * @param sha_type The SHA algorithm type |
| 57 | + */ |
| 58 | +static inline void sha_ll_continue_block(esp_sha_type sha_type) |
| 59 | +{ |
| 60 | + REG_WRITE(SHA_MODE_REG, sha_type); |
| 61 | + REG_WRITE(SHA_CONTINUE_REG, 1); |
| 62 | +} |
| 63 | + |
| 64 | +/** |
| 65 | + * @brief Start a new SHA message conversion using DMA (no initial hash in HW) |
| 66 | + * |
| 67 | + * @param sha_type The SHA algorithm type |
| 68 | + */ |
| 69 | +static inline void sha_ll_start_dma(esp_sha_type sha_type) |
| 70 | +{ |
| 71 | + REG_WRITE(SHA_MODE_REG, sha_type); |
| 72 | + REG_WRITE(SHA_DMA_START_REG, 1); |
| 73 | +} |
| 74 | + |
| 75 | +/** |
| 76 | + * @brief Continue a SHA message conversion using DMA (initial hash in HW) |
| 77 | + * |
| 78 | + * @param sha_type The SHA algorithm type |
| 79 | + */ |
| 80 | +static inline void sha_ll_continue_dma(esp_sha_type sha_type) |
| 81 | +{ |
| 82 | + REG_WRITE(SHA_MODE_REG, sha_type); |
| 83 | + REG_WRITE(SHA_DMA_CONTINUE_REG, 1); |
| 84 | +} |
| 85 | + |
| 86 | +/** |
| 87 | + * @brief Load the current hash digest to digest register |
| 88 | + * |
| 89 | + * @note Happens automatically on ESP32C6 |
| 90 | + * |
| 91 | + * @param sha_type The SHA algorithm type |
| 92 | + */ |
| 93 | +static inline void sha_ll_load(esp_sha_type sha_type) |
| 94 | +{ |
| 95 | +} |
| 96 | + |
| 97 | +/** |
| 98 | + * @brief Sets the number of message blocks to be hashed |
| 99 | + * |
| 100 | + * @note DMA operation only |
| 101 | + * |
| 102 | + * @param num_blocks Number of message blocks to process |
| 103 | + */ |
| 104 | +static inline void sha_ll_set_block_num(size_t num_blocks) |
| 105 | +{ |
| 106 | + REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks); |
| 107 | +} |
| 108 | + |
| 109 | +/** |
| 110 | + * @brief Checks if the SHA engine is currently busy hashing a block |
| 111 | + * |
| 112 | + * @return true SHA engine busy |
| 113 | + * @return false SHA engine idle |
| 114 | + */ |
| 115 | +static inline bool sha_ll_busy(void) |
| 116 | +{ |
| 117 | + return REG_READ(SHA_BUSY_REG); |
| 118 | +} |
| 119 | + |
| 120 | +/** |
| 121 | + * @brief Write a text (message) block to the SHA engine |
| 122 | + * |
| 123 | + * @param input_text Input buffer to be written to the SHA engine |
| 124 | + * @param block_word_len Number of words in block |
| 125 | + */ |
| 126 | +static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len) |
| 127 | +{ |
| 128 | + uint32_t *data_words = (uint32_t *)input_text; |
| 129 | + uint32_t *reg_addr_buf = (uint32_t *)(SHA_M_MEM); |
| 130 | + |
| 131 | + for (int i = 0; i < block_word_len; i++) { |
| 132 | + REG_WRITE(®_addr_buf[i], data_words[i]); |
| 133 | + } |
| 134 | +} |
| 135 | + |
| 136 | +/** |
| 137 | + * @brief Read the message digest from the SHA engine |
| 138 | + * |
| 139 | + * @param sha_type The SHA algorithm type |
| 140 | + * @param digest_state Buffer that message digest will be written to |
| 141 | + * @param digest_word_len Length of the message digest |
| 142 | + */ |
| 143 | +static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) |
| 144 | +{ |
| 145 | + uint32_t *digest_state_words = (uint32_t *)digest_state; |
| 146 | + const size_t REG_WIDTH = sizeof(uint32_t); |
| 147 | + |
| 148 | + for (size_t i = 0; i < digest_word_len; i++) { |
| 149 | + digest_state_words[i] = REG_READ(SHA_H_MEM + (i * REG_WIDTH)); |
| 150 | + } |
| 151 | + |
| 152 | +} |
| 153 | + |
| 154 | +/** |
| 155 | + * @brief Write the message digest to the SHA engine |
| 156 | + * |
| 157 | + * @param sha_type The SHA algorithm type |
| 158 | + * @param digest_state Message digest to be written to SHA engine |
| 159 | + * @param digest_word_len Length of the message digest |
| 160 | + */ |
| 161 | +static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) |
| 162 | +{ |
| 163 | + uint32_t *digest_state_words = (uint32_t *)digest_state; |
| 164 | + uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_MEM); |
| 165 | + |
| 166 | + for (int i = 0; i < digest_word_len; i++) { |
| 167 | + REG_WRITE(®_addr_buf[i], digest_state_words[i]); |
| 168 | + } |
| 169 | +} |
| 170 | + |
| 171 | + |
| 172 | +#ifdef __cplusplus |
| 173 | +} |
| 174 | +#endif |
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