Merge branch 'refactor/split_esp32_soc_include_folder' into 'master'

refactor(soc): sort esp32 soc headers

See merge request espressif/esp-idf!33308

Author: L-KAYA

.codespellrc

@@ -1,4 +1,4 @@
 [codespell]
 skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*,*.pem
-ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane,assertIn,registr
+ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane,assertIn,registr,oen
 write-changes = true

.gitlab/ci/host-test.yml

@@ -402,3 +402,21 @@ test_nvs_gen_check:
   script:
     - cd ${IDF_PATH}/components/nvs_flash/nvs_partition_tool
     - pytest --noconftest test_nvs_gen_check.py --junitxml=XUNIT_RESULT.xml
+
+make_sure_soc_caps_compatible_in_idf_build_apps:
+    extends:
+      - .host_test_template
+      - .rules:dev-push
+    artifacts:
+      paths:
+        - new.json
+        - base.json
+      when: always
+    when: manual
+    script:
+      - python tools/ci/idf_build_apps_dump_soc_caps.py new.json
+      - git fetch --depth=1 origin $CI_MERGE_REQUEST_DIFF_BASE_SHA
+      - git checkout -f $CI_MERGE_REQUEST_DIFF_BASE_SHA
+      - git checkout $CI_COMMIT_SHA -- tools/ci/idf_build_apps_dump_soc_caps.py
+      - python tools/ci/idf_build_apps_dump_soc_caps.py base.json
+      - diff new.json base.json

.gitlab/ci/rules.yml

@@ -225,6 +225,10 @@
   rules:
     - <<: *if-tag-release
 
+.rules:dev-push:
+  rules:
+    - <<: *if-dev-push
+
 # Do not upload caches on dev branches by default
 .rules:upload-python-cache:
   rules:

components/soc/esp32/include/soc/hwcrypto_reg.h

@@ -1,20 +1,12 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef __HWCRYPTO_REG_H__
 #define __HWCRYPTO_REG_H__
 
-#include "soc.h"
+#include "soc/soc.h"
 
 /* registers for RSA acceleration via Multiple Precision Integer ops */
 #define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)

components/soc/esp32/include/soc/nrx_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 

components/soc/esp32/include/soc/soc.h

@@ -14,7 +14,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 #define APP_CPU_NUM (1)

components/soc/esp32/register/soc/.gitkeep

@@ -8,7 +8,7 @@
 
 #warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
 
-#include "soc.h"
+#include "soc/soc.h"
 #define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x0)
 /* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
 /*description: */

components/soc/esp32/include/soc/apb_ctrl_reg.h renamed to components/soc/esp32/register/soc/apb_ctrl_reg.h

@@ -1,15 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_DPORT_REG_H_
-#define _SOC_DPORT_REG_H_
+#pragma once
 
-#include "soc.h"
+#include "soc/soc.h"
 
 #ifndef __ASSEMBLER__
-#include "dport_access.h"
+#include "soc/dport_access.h"
 #endif
 
 /* Registers defined in this header file must be accessed using special macros,
@@ -3210,8 +3209,8 @@
 #define DPORT_RECORD_PRO_PDEBUGSTATUS_V  0xFF
 #define DPORT_RECORD_PRO_PDEBUGSTATUS_S  0
 /* register layout:
- * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
- * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
+ * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for possible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
+ * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for possible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
 */
 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M  		((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V  		0x3F
@@ -4287,5 +4286,3 @@
 #define TRACEMEM_MUX_BLK0_ONLY          1
 #define TRACEMEM_MUX_BLK1_ONLY          2
 #define TRACEMEM_MUX_PROBLK1_APPBLK0    3
-
-#endif /*_SOC_DPORT_REG_H_ */