Merge branch 'feat/c61_eco3_soc_update' into 'master'

feat(soc): c61 eco3 rom and soc header update

See merge request espressif/esp-idf!39166

Author: suda-morris

components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c

@@ -81,7 +81,9 @@ bool clock_domain_pd_allowed(void)
      * necessary to check the state of CLOCK_MODEM to determine MODEM domain on
      * or off. The clock and reset of digital peripherals are managed through
      * PCR, with TOP domain similar to MODEM domain. */
+#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED
     sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } };
+#endif
 #if SOC_WIFI_SUPPORTED
     modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC % 32);
     modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_BB % 32);

components/esp_hw_support/port/esp32c61/Kconfig.hw_support

@@ -1,6 +1,6 @@
 choice ESP32C61_REV_MIN
     prompt "Minimum Supported ESP32-C61 Revision"
-    default ESP32C61_REV_MIN_0
+    default ESP32C61_REV_MIN_100
     help
         Required minimum chip revision. ESP-IDF will check for it and
         reject to boot if the chip revision fails the check.
@@ -9,13 +9,13 @@ choice ESP32C61_REV_MIN
         The complied binary will only support chips above this revision,
         this will also help to reduce binary size.
 
-    config ESP32C61_REV_MIN_0
-        bool "Rev v0.0"
+    config ESP32C61_REV_MIN_100
+        bool "Rev v1.0"
 endchoice
 
 config ESP32C61_REV_MIN_FULL
     int
-    default 0 if ESP32C61_REV_MIN_0
+    default 100 if ESP32C61_REV_MIN_100
 
 config ESP_REV_MIN_FULL
     int
@@ -25,15 +25,15 @@ config ESP_REV_MIN_FULL
     # MAX Revision
     #
 
-    comment "Maximum Supported ESP32-C61 Revision (Rev v0.99)"
+    comment "Maximum Supported ESP32-C61 Revision (Rev v1.99)"
     # Maximum revision that IDF supports.
     # It can not be changed by user.
     # Only Espressif can change it when a new version will be supported in IDF.
     # Supports all chips starting from ESP32C61_REV_MIN_FULL to ESP32C61_REV_MAX_FULL
 
 config ESP32C61_REV_MAX_FULL
     int
-    default 99
+    default 199
     # keep in sync the "Maximum Supported Revision" description with this value
 
 config ESP_REV_MAX_FULL
@@ -53,6 +53,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL
 
 config ESP_EFUSE_BLOCK_REV_MAX_FULL
     int
-    default 99
+    default 199
     comment "Maximum Supported ESP32-C61 eFuse Block Revision (eFuse Block Rev v0.99)"
     # The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL

components/esp_rom/CMakeLists.txt

@@ -67,10 +67,6 @@ if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG OR CONFIG_ESP_ROM_HAS_CACHE_WRITEBAC
     list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c")
 endif()
 
-if(CONFIG_ESP_ROM_CACHE_WB_INVLD_LOW_RANGE)
-    list(APPEND sources "patches/esp_rom_cache_esp32c61.c")
-endif()
-
 if(CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG)
     list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S")
 endif()

components/esp_rom/esp32c61/Kconfig.soc_caps.in

@@ -107,10 +107,6 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
     bool
     default y
 
-config ESP_ROM_CACHE_WB_INVLD_LOW_RANGE
-    bool
-    default y
-
 config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
     bool
     default y

components/esp_rom/esp32c61/esp_rom_caps.h

@@ -32,5 +32,4 @@
 #define ESP_ROM_HAS_SW_FLOAT                (1) // ROM has libgcc software floating point emulation functions
 #define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
-#define ESP_ROM_CACHE_WB_INVLD_LOW_RANGE    (1) // ROM `Cache_WriteBack_Addr` and `Cache_Invalidate_Addr` can only access low vaddr parts
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.

components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld

@@ -1,14 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-/* ROM function interface esp32c61.rom.coexist.ld for esp32c61
- *
- *
- * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
- *
- * Compatible with ROM where ECO version equal or greater to 0.
+
+/* ROM function interface
  *
  * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  */
@@ -35,7 +31,7 @@ coex_hw_timer_set = 0x40000a64;
 coex_schm_interval_set = 0x40000a68;
 coex_schm_lock = 0x40000a6c;
 coex_schm_unlock = 0x40000a70;
-/*coex_status_get = 0x40000a74;*/
+coex_status_get = 0x40000a74;
 coex_wifi_release = 0x40000a78;
 esp_coex_ble_conn_dynamic_prio_get = 0x40000a7c;
 /* Data (.data, .bss, .rodata) */

components/esp_rom/esp32c61/ld/esp32c61.rom.ld

@@ -1,14 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-/* ROM function interface esp32c61.rom.ld for esp32c61
- *
- *
- * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
- *
- * Compatible with ROM where ECO version equal or greater to 0.
+
+/* ROM function interface
  *
  * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  */
@@ -54,8 +50,6 @@ software_reset_cpu = 0x40000098;
 ets_clk_assist_debug_clock_enable = 0x4000009c;
 clear_super_wdt_reset_flag = 0x400000a0;
 disable_default_watchdog = 0x400000a4;
-esp_rom_set_rtc_wake_addr = 0x400000a8;
-esp_rom_get_rtc_wake_addr = 0x400000ac;
 send_packet = 0x400000b0;
 recv_packet = 0x400000b4;
 GetUartDevice = 0x400000b8;
@@ -192,9 +186,9 @@ MMU_Set_Page_Mode = 0x40000624;
 MMU_Get_Page_Mode = 0x40000628;
 Cache_Sync_Items = 0x4000062c;
 Cache_Op_Addr = 0x40000630;
-/*Cache_Invalidate_Addr = 0x40000634; rom version API has issue that unable to access higher vaddr range, use IDF patch */
+Cache_Invalidate_Addr = 0x40000634;
 Cache_Clean_Addr = 0x40000638;
-/*Cache_WriteBack_Addr = 0x4000063c; rom version API has issue that unable to access higher vaddr range, use IDF patch */
+Cache_WriteBack_Addr = 0x4000063c;
 Cache_WriteBack_Invalidate_Addr = 0x40000640;
 Cache_Invalidate_All = 0x40000644;
 Cache_Clean_All = 0x40000648;
@@ -369,7 +363,6 @@ ets_efuse_jtag_disabled = 0x400007fc;
 ets_efuse_usb_print_is_disabled = 0x40000800;
 ets_efuse_usb_download_mode_disabled = 0x40000804;
 ets_efuse_usb_device_disabled = 0x40000808;
-ets_efuse_secure_boot_fast_wake_enabled = 0x4000080c;
 
 
 /***************************************
@@ -393,3 +386,60 @@ usb_serial_device_rx_one_char = 0x40000a20;
 usb_serial_device_rx_one_char_block = 0x40000a24;
 usb_serial_device_tx_flush = 0x40000a28;
 usb_serial_device_tx_one_char = 0x40000a2c;
+
+
+/***************************************
+ Group lldesc
+ ***************************************/
+
+/* Functions */
+lldesc_build_chain = 0x400014dc;
+
+
+/***************************************
+ Group sip
+ ***************************************/
+
+/* Functions */
+sip_after_tx_complete = 0x400014e0;
+sip_alloc_to_host_evt = 0x400014e4;
+sip_download_begin = 0x400014e8;
+sip_get_ptr = 0x400014ec;
+sip_get_state = 0x400014f0;
+sip_init_attach = 0x400014f4;
+sip_install_rx_ctrl_cb = 0x400014f8;
+sip_install_rx_data_cb = 0x400014fc;
+sip_is_active = 0x40001500;
+sip_post_init = 0x40001504;
+sip_reclaim_from_host_cmd = 0x40001508;
+sip_reclaim_tx_data_pkt = 0x4000150c;
+sip_send = 0x40001510;
+sip_to_host_chain_append = 0x40001514;
+sip_to_host_evt_send_done = 0x40001518;
+
+
+/***************************************
+ Group slc
+ ***************************************/
+
+/* Functions */
+slc_add_credits = 0x4000151c;
+slc_enable = 0x40001520;
+slc_from_host_chain_fetch = 0x40001524;
+slc_from_host_chain_recycle = 0x40001528;
+slc_has_pkt_to_host = 0x4000152c;
+slc_init_attach = 0x40001530;
+slc_init_credit = 0x40001534;
+slc_reattach = 0x40001538;
+slc_send_to_host_chain = 0x4000153c;
+slc_set_host_io_max_window = 0x40001540;
+slc_to_host_chain_recycle = 0x40001544;
+
+
+/***************************************
+ Group recovery_bootloader
+ ***************************************/
+
+/* Functions */
+ets_get_bootloader_offset = 0x40001548;
+ets_set_bootloader_offset = 0x4000154c;

components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld

@@ -1,14 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-/* ROM function interface esp32c61.rom.net80211.ld for esp32c61
- *
- *
- * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457
- *
- * Compatible with ROM where ECO version equal or greater to 0.
+
+/* ROM function interface
  *
  * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  */
@@ -40,7 +36,7 @@ ieee80211_encap_esfbuf = 0x40000ac8;
 ieee80211_is_tx_allowed = 0x40000acc;
 ieee80211_output_pending_eb = 0x40000ad0;
 ieee80211_output_process = 0x40000ad4;
-/*ieee80211_set_tx_desc = 0x40000ad8;*/
+ieee80211_set_tx_desc = 0x40000ad8;
 ieee80211_classify = 0x40000adc;
 ieee80211_copy_eb_header = 0x40000ae0;
 ieee80211_recycle_cache_eb = 0x40000ae4;
@@ -60,12 +56,12 @@ ieee80211_find_ext_elem = 0x40000b18;
 ieee80211_find_ie = 0x40000b1c;
 ieee80211_find_ext_ie = 0x40000b20;
 ieee80211_merge_mbssid_profile = 0x40000b24;
-/*ieee80211_encap_esfbuf_htc = 0x40000b28;*/
+ieee80211_encap_esfbuf_htc = 0x40000b28;
 wifi_get_macaddr = 0x40000b2c;
 wifi_rf_phy_disable = 0x40000b30;
 wifi_rf_phy_enable = 0x40000b34;
 wifi_is_started = 0x40000b38;
-/*sta_input = 0x40000b3c;*/
+sta_input = 0x40000b3c;
 sta_rx_eapol = 0x40000b40;
 sta_reset_beacon_timeout = 0x40000b44;
 sta_get_beacon_timeout = 0x40000b48;