You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
* @brief Input RMII Clock from external. EMAC Clock GPIO number needs to be configured when this option is selected.
37
27
*
38
-
* @note MAC will get RMII clock from outside. Note that ESP32 only supports GPIO0 to input the RMII clock.
28
+
* @note See components/soc/esp32(*)/emac_periph.c for available GPIO numbers.
39
29
*
40
30
*/
41
31
EMAC_CLK_EXT_IN,
42
32
43
33
/**
44
34
* @brief Output RMII Clock from internal (A/M)PLL Clock. EMAC Clock GPIO number needs to be configured when this option is selected.
45
35
*
46
-
*/
47
-
EMAC_CLK_OUT
48
-
} emac_rmii_clock_mode_t;
49
-
50
-
#ifCONFIG_IDF_TARGET_ESP32
51
-
/**
52
-
* @brief RMII Clock GPIO number Options for ESP32
53
-
*
54
-
* @warning If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output as it would result in clock instability.
55
-
*
56
-
*/
57
-
typedefenum {
58
-
/**
59
-
* @brief MAC will get RMII clock from outside at this GPIO.
60
-
*
61
-
* @note ESP32 only supports GPIO0 to input the RMII clock.
62
-
*
63
-
*/
64
-
EMAC_CLK_IN_GPIO=0,
65
-
66
-
/**
67
-
* @brief Output RMII Clock from internal APLL Clock available at GPIO0
36
+
* @warning ESP32 Errata: If you want the Ethernet to work with Wi-Fi or BT, don’t select ESP32 as RMII CLK output as it would result in clock instability.
37
+
* Applicable only to ESP32, other ESP32 SoCs are not affected.
68
38
*
69
-
* @note GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure GPIO0 to output a 50MHz clock.
70
-
* In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock may not work well with your PHY chip.
71
-
*
72
-
*/
73
-
EMAC_APPL_CLK_OUT_GPIO=0,
74
-
75
-
/**
76
-
* @brief Output RMII Clock from internal APLL Clock available at GPIO16
77
-
*
78
-
*/
79
-
EMAC_CLK_OUT_GPIO=16,
80
-
81
-
/**
82
-
* @brief Inverted Output RMII Clock from internal APLL Clock available at GPIO17
39
+
* @note See components/soc/esp32(*)/emac_periph.c for available GPIO numbers.
83
40
*
84
41
*/
85
-
EMAC_CLK_OUT_180_GPIO=17
86
-
} emac_rmii_clock_gpio_t;
87
-
#else
88
-
/**
89
-
* @brief RMII Clock GPIO number
90
-
*
91
-
*/
92
-
typedefintemac_rmii_clock_gpio_t;
93
-
#endif// CONFIG_IDF_TARGET_ESP32
42
+
EMAC_CLK_OUT
43
+
} emac_rmii_clock_mode_t;
94
44
95
45
/**
96
46
* @brief Ethernet MAC Clock Configuration
@@ -102,8 +52,8 @@ typedef union {
102
52
// Reserved for GPIO number, clock source, etc. in MII mode
intsmi_mdc_gpio_num __attribute__((deprecated("Please use smi_gpio instead"))); /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */
172
-
intsmi_mdio_gpio_num __attribute__((deprecated("Please use smi_gpio instead"))); /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */
Copy file name to clipboardExpand all lines: docs/en/api-reference/network/esp_eth.rst
+6-16Lines changed: 6 additions & 16 deletions
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -130,15 +130,8 @@ The Ethernet driver is composed of two parts: MAC and PHY.
130
130
131
131
One of the obvious differences between MII and RMII is signal consumption. MII usually costs up to 18 signals, while the RMII interface can reduce the consumption to 9.
132
132
133
-
.. only:: esp32
134
-
135
-
.. note::
136
-
ESP-IDF only supports the RMII interface. Therefore, always set :cpp:member:`eth_esp32_emac_config_t::interface` to :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII` or always select ``CONFIG_ETH_PHY_INTERFACE_RMII`` in the Kconfig option :ref:`CONFIG_ETH_PHY_INTERFACE`.
137
-
138
-
.. only:: not esp32
139
-
140
-
.. note::
141
-
ESP-IDF only supports the RMII interface. Therefore, always set :cpp:member:`eth_esp32_emac_config_t::interface` to :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII`.
133
+
.. note::
134
+
ESP-IDF only supports the RMII interface. Therefore, always set :cpp:member:`eth_esp32_emac_config_t::interface` to :cpp:enumerator:`eth_data_interface_t::EMAC_DATA_INTERFACE_RMII`.
142
135
143
136
In RMII mode, both the receiver and transmitter signals are referenced to the ``REF_CLK``. ``REF_CLK`` **must be stable during any access to PHY and MAC**. Generally, there are three ways to generate the ``REF_CLK`` depending on the PHY device in your design:
144
137
@@ -150,15 +143,12 @@ The Ethernet driver is composed of two parts: MAC and PHY.
150
143
151
144
.. only:: esp32
152
145
153
-
.. note::
154
-
The ``REF_CLK`` can be also configured via Project Configuration when :cpp:class:`eth_esp32_emac_config_t` is initialized using :c:macro:`ETH_ESP32_EMAC_DEFAULT_CONFIG` macro. In the Project Configuration, choose appropriately ``CONFIG_ETH_RMII_CLK_INPUT`` or ``CONFIG_ETH_RMII_CLK_OUTPUT`` option under :ref:`CONFIG_ETH_RMII_CLK_MODE` configuration based on your design as discussed above.
155
-
156
146
.. warning::
157
-
If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_OUT` (or ``CONFIG_ETH_RMII_CLK_OUTPUT`` is selected), then ``GPIO0`` can be used to output the ``REF_CLK`` signal. See :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_APPL_CLK_OUT_GPIO` or :ref:`CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0` for more information.
147
+
If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_OUT`, internal Audio PLL clock is used as a source of 50 MHz clock. Hence be sure it is not in collision with I2S bus configuration.
158
148
159
-
What is more, if you are not using PSRAM in your design, GPIO16 and GPIO17 are also available to output the reference clock signal. See :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_CLK_OUT_GPIO` and :cpp:enumerator:`emac_rmii_clock_gpio_t::EMAC_CLK_OUT_180_GPIO` or :ref:`CONFIG_ETH_RMII_CLK_OUT_GPIO` for more information.
149
+
When internal clock is selected, then ``GPIO0`` can be used to output the ``REF_CLK`` signal. However, the clock is outputted directly to the GPIO in this particular case and so it does not have direct relationship with EMAC peripheral. Sometimes this configuration may not work well with your PHY chip. If you are not using PSRAM in your design, GPIO16 and GPIO17 are also available to output the reference clock signal. The source of clock is the same (APLL) but these signals are routed from EMAC peripheral.
160
150
161
-
If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN` (or ``CONFIG_ETH_RMII_CLK_INPUT`` is selected), then ``GPIO0`` is the only choice to input the ``REF_CLK`` signal. Please note that ``GPIO0`` is also an important strapping GPIO on ESP32. If GPIO0 samples a low level during power-up, ESP32 will go into download mode. The system will get halted until a manually reset. The workaround for this issue is disabling the ``REF_CLK`` in hardware by default so that the strapping pin is not interfered by other signals in the boot stage. Then, re-enable the ``REF_CLK`` in the Ethernet driver installation stage.
151
+
If the RMII clock mode is configured to :cpp:enumerator:`emac_rmii_clock_mode_t::EMAC_CLK_EXT_IN`, then ``GPIO0`` is the only choice to input the ``REF_CLK`` signal. Please note that ``GPIO0`` is also an important strapping GPIO on ESP32. If GPIO0 samples a low level during power-up, ESP32 will go into download mode. The system will get halted until a manually reset. The workaround for this issue is disabling the ``REF_CLK`` in hardware by default so that the strapping pin is not interfered by other signals in the boot stage. Then, re-enable the ``REF_CLK`` in the Ethernet driver installation stage.
162
152
163
153
The ways to disable the ``REF_CLK`` signal can be:
164
154
@@ -167,7 +157,7 @@ The Ethernet driver is composed of two parts: MAC and PHY.
167
157
* Force the PHY device to reset status (as the case **a** in the picture). **This could fail for some PHY device** (i.e., it still outputs signals to GPIO0 even in reset state).
168
158
169
159
.. warning::
170
-
If you want the **Ethernet to work with Wi-Fi**, don’t select ESP32 as source of ``REF_CLK`` as it would result in ``REF_CLK`` instability. Either disable Wi-Fi or use a PHY or an external oscillator as the ``REF_CLK`` source.
160
+
If you want the **Ethernet to work with Wi-Fi or Bluetooth**, don’t select ESP32 as source of ``REF_CLK`` as it would result in ``REF_CLK`` instability. Either disable Wi-Fi or use a PHY or an external oscillator as the ``REF_CLK`` source.
Copy file name to clipboardExpand all lines: docs/en/migration-guides/release-6.x/6.0/networking.rst
+26Lines changed: 26 additions & 0 deletions
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -16,3 +16,29 @@ Usage example:
16
16
.. code-block:: c
17
17
18
18
esp_eth_phy_802_3_reset_hw(phy_802_3);
19
+
20
+
21
+
Removed RMII Clock Kconfig Options
22
+
----------------------------------
23
+
24
+
Removed the following RMII clock Kconfig options from `components/esp_eth`. Clock configuration is now handled exclusively through EMAC config structures.
emac_config.clock_config.rmii.clock_mode = EMAC_CLK_OUT; // or EMAC_CLK_EXT_IN
40
+
emac_config.clock_config.rmii.clock_gpio = 0; // GPIO0 for ESP32
41
+
42
+
43
+
**Impact**: Applications using ``ETH_ESP32_EMAC_DEFAULT_CONFIG()`` continue to work. Custom clock configurations must be set explicitly in the EMAC config structure or use the `Ethernet Init component <https://components.espressif.com/components/espressif/ethernet_init>`_.
0 commit comments