feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5

Author: songruo

components/esp_driver_gpio/include/driver/gpio.h

@@ -419,23 +419,25 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
   * signal or the IO MUX/GPIO configuration is modified (including input enable, output enable, output value,
   * function, and drive strength values). This function can be used to retain the state of GPIOs when the power
   * domain of where GPIO/IOMUX belongs to becomes off. For example, chip or system is reset (e.g. watchdog
-  * time-out, deep-sleep events are triggered), or peripheral power-down in light-sleep.
+  * time-out, Deep-sleep events are triggered), or peripheral power-down in Light-sleep.
   *
   * This function works in both input and output modes, and only applicable to output-capable GPIOs.
   * If this function is enabled:
   *   in output mode: the output level of the GPIO will be locked and can not be changed.
   *   in input mode: the input read value can still reflect the changes of the input signal.
   *
+  * Power down or call `gpio_hold_dis` will disable this function.
+  *
   * Please be aware that,
   *
-  * On ESP32P4, the states of IOs can not be hold after waking up from Deep-sleep.
+  * 1. USB pads cannot hold at low level after waking up from Deep-sleep. The USB related registers are reset, so the USB pull-up is back.
+  *
+  * 2. For ESP32-P4 rev < 3.0, the states of IOs can not be hold after waking up from Deep-sleep.
   *
-  * Additionally, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep.
+  * 3. For ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep.
   * Even if this function is enabled, the digital GPIO will be reset to its default state when the chip wakes up from
   * Deep-sleep. If you want to hold the state of a digital GPIO during Deep-sleep, please call `gpio_deep_sleep_hold_en`.
   *
-  * Power down or call `gpio_hold_dis` will disable this function.
-  *
   * @param gpio_num GPIO number, only support output-capable GPIOs
   *
   * @return
@@ -463,7 +465,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num);
   */
 esp_err_t gpio_hold_dis(gpio_num_t gpio_num);
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 /**
   * @brief Enable all digital gpio pads hold function during Deep-sleep.
   *
@@ -487,7 +489,7 @@ void gpio_deep_sleep_hold_en(void);
   * @brief Disable all digital gpio pads hold function during Deep-sleep.
   */
 void gpio_deep_sleep_hold_dis(void);
-#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 
 #if SOC_GPIO_SUPPORT_FORCE_HOLD
 /**

components/esp_driver_gpio/src/gpio.c

@@ -8,13 +8,13 @@
 #include "esp_err.h"
 #include "freertos/FreeRTOS.h"
 #include "esp_heap_caps.h"
+#include "sdkconfig.h"
 #include "driver/gpio.h"
 #include "driver/rtc_io.h"
 #include "soc/interrupts.h"
 #if !CONFIG_FREERTOS_UNICORE
 #include "esp_ipc.h"
 #endif
-
 #include "soc/soc_caps.h"
 #include "soc/gpio_periph.h"
 #include "esp_log.h"
@@ -775,7 +775,7 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num)
     return ret;
 }
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 void gpio_deep_sleep_hold_en(void)
 {
     portENTER_CRITICAL(&gpio_context.gpio_spinlock);
@@ -789,7 +789,7 @@ void gpio_deep_sleep_hold_dis(void)
     gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal);
     portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
 }
-#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 
 #if SOC_GPIO_SUPPORT_FORCE_HOLD
 esp_err_t IRAM_ATTR gpio_force_hold_all()

components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c

@@ -884,7 +884,7 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
 }
 #endif
 
-#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+#if SOC_DEEP_SLEEP_SUPPORTED
 // Pick one digital IO for each target to test is enough
 static void gpio_deep_sleep_hold_test_first_stage(void)
 {
@@ -902,7 +902,9 @@ static void gpio_deep_sleep_hold_test_first_stage(void)
         .pull_up_en = GPIO_PULLUP_DISABLE,
     };
     TEST_ESP_OK(gpio_config(&io_conf));
-    TEST_ESP_OK(gpio_set_level(io_num, 0));
+
+    const bool initial_level = gpio_get_level(io_num);
+    TEST_ESP_OK(gpio_set_level(io_num, !initial_level));
 
     // Enable global persistence
     TEST_ESP_OK(gpio_hold_en(io_num));
@@ -911,6 +913,10 @@ static void gpio_deep_sleep_hold_test_first_stage(void)
     // Extra step is required, so that all digital IOs can automatically get held when entering Deep-sleep
     gpio_deep_sleep_hold_en();
 #endif
+    vTaskDelay(pdMS_TO_TICKS(200));
+    TEST_ESP_OK(gpio_set_level(io_num, initial_level));
+    TEST_ASSERT_EQUAL_INT(!initial_level, gpio_get_level(io_num));
+    vTaskDelay(pdMS_TO_TICKS(200));
 
     esp_deep_sleep_start();
 }
@@ -921,16 +927,31 @@ static void gpio_deep_sleep_hold_test_second_stage(void)
     // Check reset reason is waking up from deepsleep
     TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
 
-    // Pin should stay at low level after the deep sleep
-    TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
+    bool level = gpio_get_level(io_num);
     // Set level should not take effect since hold is still active (and the INPUT_OUTPUT mode should still be held)
-    TEST_ESP_OK(gpio_set_level(io_num, 1));
-    TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
+    TEST_ESP_OK(gpio_set_level(io_num, !level));
+    TEST_ASSERT_EQUAL_INT(level, gpio_get_level(io_num));
+#endif
 
 #if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     gpio_deep_sleep_hold_dis();
 #endif
     TEST_ESP_OK(gpio_hold_dis(io_num));
+
+    gpio_config_t io_conf = {
+        .intr_type = GPIO_INTR_DISABLE,
+        .mode = GPIO_MODE_INPUT_OUTPUT,
+        .pin_bit_mask = (1ULL << io_num),
+        .pull_down_en = GPIO_PULLDOWN_DISABLE,
+        .pull_up_en = GPIO_PULLUP_DISABLE,
+    };
+    TEST_ESP_OK(gpio_config(&io_conf));
+
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
+    // Check that the hold level after wakeup is the level before entering deep sleep
+    TEST_ASSERT_EQUAL_INT(!level, gpio_get_level(io_num));
+#endif
 }
 
 /*
@@ -942,4 +963,4 @@ static void gpio_deep_sleep_hold_test_second_stage(void)
 TEST_CASE_MULTIPLE_STAGES("GPIO_deep_sleep_output_hold_test", "[gpio]",
                           gpio_deep_sleep_hold_test_first_stage,
                           gpio_deep_sleep_hold_test_second_stage)
-#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+#endif // SOC_DEEP_SLEEP_SUPPORTED

components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h

@@ -39,6 +39,7 @@ extern "C" {
 #define TEST_GPIO_EXT_IN_IO                (3)
 #define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
 #define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC250_IDX)
+#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN      (28)
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define TEST_GPIO_EXT_OUT_IO               (2)
 #define TEST_GPIO_EXT_IN_IO                (3)

components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c

@@ -278,7 +278,7 @@ TEST_CASE("RTCIO_interrupt_test", "[rtcio]")
 #endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
 #endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
-#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+#if SOC_DEEP_SLEEP_SUPPORTED
 // It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
 // Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
 // The default configuration of these pads is low level
@@ -311,8 +311,10 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
     int io_num = s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX];
     // Check reset reason is waking up from deepsleep
     TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
     // Pin should stay at high level after the deep sleep
     TEST_ASSERT_EQUAL_INT(1, gpio_get_level(io_num));
+#endif
 
     gpio_hold_dis(io_num);
 }
@@ -326,4 +328,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
 TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]",
                           rtcio_deep_sleep_hold_test_first_stage,
                           rtcio_deep_sleep_hold_test_second_stage)
-#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
+#endif // SOC_DEEP_SLEEP_SUPPORTED

components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h

@@ -162,6 +162,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
     GPIO_NUM_15,   //GPIO15
 };
 #define TEST_RTCIO_INTR_PIN_INDEX       2 // IO2
+#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO5
 #elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5
 // Has no input-only rtcio pins, all pins support pull-up/down
 #define RTCIO_SUPPORT_PU_PD(num)    1

components/esp_hw_support/include/esp_private/esp_sleep_internal.h

@@ -97,7 +97,7 @@ esp_err_t esp_sleep_acquire_lp_use_xtal(void);
 esp_err_t esp_sleep_release_lp_use_xtal(void);
 #endif
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 /**
  * @brief Isolate all digital IOs except those that are held during deep sleep
  *

components/esp_hw_support/port/esp32p4/private_include/pmu_param.h

@@ -11,6 +11,7 @@
 #include <esp_types.h>
 #include "soc/pmu_struct.h"
 #include "hal/pmu_hal.h"
+#include "sdkconfig.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -330,6 +331,7 @@ typedef struct {
 } pmu_sleep_digital_config_t;
 
 
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 #define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) {            \
     .syscntl = {                                                        \
         .dig_pad_slp_sel = 0,                                           \
@@ -343,6 +345,19 @@ typedef struct {
         .lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
     }                                                                   \
 }
+#else // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) {            \
+    .syscntl = {                                                        \
+        .dig_pad_slp_sel = 0,                                           \
+    }                                                                   \
+}
+
+#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) {            \
+    .syscntl = {                                                        \
+        .dig_pad_slp_sel = 0,                                           \
+    }                                                                   \
+}
+#endif
 
 typedef struct {
     struct {

components/esp_hw_support/sleep_gpio.c

@@ -170,7 +170,7 @@ void esp_sleep_enable_gpio_switch(bool enable)
     }
 }
 
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
 {
     gpio_hal_context_t gpio_hal = {
@@ -225,7 +225,7 @@ IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
         }
     }
 }
-#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
 
 #if SOC_DEEP_SLEEP_SUPPORTED
 void esp_deep_sleep_wakeup_io_reset(void)

components/esp_hw_support/sleep_modes.c

@@ -907,7 +907,7 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
     }
 #endif
     if (deep_sleep) {
-#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
         esp_sleep_isolate_digital_gpio();
 #endif