Merge branch 'feat/ap_quad_psram_ecc_c61_c5' into 'master'

psram: add quad psram error correcting code (ECC) feature on ESP32C61/C5

Closes IDF-12027

See merge request espressif/esp-idf!36465

Author: Icarus113

components/esp_psram/device/esp_psram_impl_ap_quad.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,7 +16,7 @@
 #include "esp_private/mspi_timing_tuning.h"
 #include "esp_private/esp_gpio_reserve.h"
 #include "hal/psram_ctrlr_ll.h"
-#include "esp_quad_psram_defs.h"
+#include "esp_quad_psram_defs_ap.h"
 #include "soc/soc_caps.h"
 
 static const char* TAG = "quad_psram";
@@ -31,7 +31,7 @@ uint8_t esp_psram_impl_get_cs_io(void)
     return s_psram_cs_io;
 }
 
-void psram_exec_cmd(int spi_num, psram_hal_cmd_mode_t mode,
+void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
                     uint32_t cmd, int cmd_bit_len,
                     uint32_t addr, int addr_bit_len,
                     int dummy_bits,
@@ -60,7 +60,7 @@ void psram_exec_cmd(int spi_num, psram_hal_cmd_mode_t mode,
 static void psram_disable_qio_mode(int spi_num)
 {
     psram_exec_cmd(spi_num, PSRAM_HAL_CMD_QPI,
-                   PSRAM_EXIT_QMODE, 8,              /* command and command bit len*/
+                   PSRAM_QUAD_EXIT_QMODE, 8,              /* command and command bit len*/
                    0, 0,                             /* address and address bit len*/
                    0,                                /* dummy bit len */
                    NULL, 0,                          /* tx data and tx bit len*/
@@ -72,10 +72,10 @@ static void psram_disable_qio_mode(int spi_num)
 //TODO IDF-4307
 //switch psram burst length(32 bytes or 1024 bytes)
 //datasheet says it should be 1024 bytes by default
-static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode)
+static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
 {
     psram_exec_cmd(spi_num, mode,
-                   PSRAM_SET_BURST_LEN, 8,           /* command and command bit len*/
+                   PSRAM_QUAD_SET_BURST_LEN, 8,           /* command and command bit len*/
                    0, 0,                             /* address and address bit len*/
                    0,                                /* dummy bit len */
                    NULL, 0,                          /* tx data and tx bit len*/
@@ -88,7 +88,7 @@ static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode)
 static void psram_reset_mode(int spi_num)
 {
     psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
-                   PSRAM_RESET_EN, 8,                /* command and command bit len*/
+                   PSRAM_QUAD_RESET_EN, 8,                /* command and command bit len*/
                    0, 0,                             /* address and address bit len*/
                    0,                                /* dummy bit len */
                    NULL, 0,                          /* tx data and tx bit len*/
@@ -97,7 +97,7 @@ static void psram_reset_mode(int spi_num)
                    false);                           /* whether is program/erase operation */
 
     psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
-                   PSRAM_RESET, 8,                   /* command and command bit len*/
+                   PSRAM_QUAD_RESET, 8,                   /* command and command bit len*/
                    0, 0,                             /* address and address bit len*/
                    0,                                /* dummy bit len */
                    NULL, 0,                          /* tx data and tx bit len*/
@@ -144,7 +144,7 @@ bool psram_support_wrap_size(uint32_t wrap_size)
 static void psram_read_id(int spi_num, uint8_t* dev_id, int id_bits)
 {
     psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
-                   PSRAM_DEVICE_ID, 8,               /* command and command bit len*/
+                   PSRAM_QUAD_DEVICE_ID, 8,               /* command and command bit len*/
                    0, 24,                            /* address and address bit len*/
                    0,                                /* dummy bit len */
                    NULL, 0,                          /* tx data and tx bit len*/
@@ -157,7 +157,7 @@ static void psram_read_id(int spi_num, uint8_t* dev_id, int id_bits)
 static void psram_enable_qio_mode(int spi_num)
 {
     psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI,
-                   PSRAM_ENTER_QMODE, 8,             /* command and command bit len*/
+                   PSRAM_QUAD_ENTER_QMODE, 8,             /* command and command bit len*/
                    0, 0,                             /* address and address bit len*/
                    0,                                /* dummy bit len */
                    NULL, 0,                          /* tx data and tx bit len*/
@@ -168,14 +168,56 @@ static void psram_enable_qio_mode(int spi_num)
 
 static void psram_set_cs_timing(void)
 {
-    psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_HOLD_VAL);
-    psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_SETUP_VAL);
+    psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_HOLD_VAL);
+    psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_SETUP_VAL);
+#if CONFIG_SPIRAM_ECC_ENABLE
+    psram_ctrlr_ll_set_ecc_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_ECC_HOLD_TIME_VAL);
+#endif
 }
 
+#if CONFIG_SPIRAM_ECC_ENABLE
+static void s_mspi_ecc_show_info(void)
+{
+    for (int i = 0; i < PSRAM_CTRLR_LL_PMS_REGION_NUMS; i++) {
+        ESP_EARLY_LOGV(TAG, "region[%d] addr: 0x%08x", i, psram_ctrlr_ll_get_pms_region_start_addr(PSRAM_CTRLR_LL_MSPI_ID_0, i));
+        ESP_EARLY_LOGV(TAG, "region[%d] size: 0x%08x", i, psram_ctrlr_ll_get_pms_region_size(PSRAM_CTRLR_LL_MSPI_ID_0, i));
+    }
+
+    uint32_t page_size = psram_ctrlr_ll_get_page_size(PSRAM_CTRLR_LL_MSPI_ID_0);
+    ESP_EARLY_LOGV(TAG, "ECC page size: %d", page_size);
+}
+
+/**
+ * Enable error correcting code feature
+ *
+ * Can add an input parameter for selecting ECC mode if needed
+ */
+static void s_configure_psram_ecc(void)
+{
+    psram_ctrlr_ll_set_ecc_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_ECC_MODE_16TO18);
+    psram_ctrlr_ll_enable_skip_page_corner(PSRAM_CTRLR_LL_MSPI_ID_0, true);
+    psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_0, true);
+    psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_PAGE_SIZE);
+    psram_ctrlr_ll_enable_ecc_addr_conversion(PSRAM_CTRLR_LL_MSPI_ID_0, true);
+
+    /**
+     * Enable ECC region 0 (ACE0)
+     * Default: ACE0 range: 0 ~ 256MB
+     * For current Quad PSRAM, ACE0 is enough
+     */
+    psram_ctrlr_ll_set_pms_region_start_addr(PSRAM_CTRLR_LL_MSPI_ID_0, 0, 0);
+    psram_ctrlr_ll_set_pms_region_size(PSRAM_CTRLR_LL_MSPI_ID_0, 0, 4096);
+    psram_ctrlr_ll_set_pms_region_attr(PSRAM_CTRLR_LL_MSPI_ID_0, 0, PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE | PSRAM_CTRLR_LL_PMS_ATTR_READABLE);
+    psram_ctrlr_ll_enable_pms_region_ecc(PSRAM_CTRLR_LL_MSPI_ID_0, 0, true);
+    ESP_EARLY_LOGI(TAG, "ECC is enabled");
+    s_mspi_ecc_show_info();
+}
+#endif
+
 static void psram_gpio_config(void)
 {
     //CS1
-    uint8_t cs1_io = PSRAM_CS_IO;
+    uint8_t cs1_io = PSRAM_QUAD_CS_IO;
     if (cs1_io == MSPI_IOMUX_PIN_NUM_CS1) {
         gpio_ll_func_sel(&GPIO, cs1_io, FUNC_SPICS1_SPICS1);
     } else {
@@ -185,7 +227,7 @@ static void psram_gpio_config(void)
     s_psram_cs_io = cs1_io;
 
     //WP HD
-    uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
+    uint8_t wp_io = PSRAM_QUAD_SPIWP_SD3_IO;
 #if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
     const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
     if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
@@ -224,7 +266,7 @@ static void s_config_psram_clock(void)
 bool s_check_aps3204_2tmode(void)
 {
     uint64_t full_eid = 0;
-    psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_EID_BITS_NUM);
+    psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_QUAD_EID_BITS_NUM);
 
     bool is_2t = false;
     uint32_t eid_47_16 = __builtin_bswap32((full_eid >> 16) & UINT32_MAX);
@@ -240,6 +282,9 @@ esp_err_t esp_psram_impl_enable(void)
 {
     psram_gpio_config();
     psram_set_cs_timing();
+#if CONFIG_SPIRAM_ECC_ENABLE
+    s_configure_psram_ecc();
+#endif
 
 #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
     //enter MSPI slow mode to init PSRAM device registers
@@ -250,31 +295,31 @@ esp_err_t esp_psram_impl_enable(void)
 
     //We use SPI1 to init PSRAM
     psram_disable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1);
-    psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_ID_BITS_NUM);
-    if (!PSRAM_IS_VALID(psram_id)) {
+    psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_QUAD_ID_BITS_NUM);
+    if (!PSRAM_QUAD_IS_VALID(psram_id)) {
         /* 16Mbit psram ID read error workaround:
          * treat the first read id as a dummy one as the pre-condition,
          * Send Read ID command again
          */
-        psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_ID_BITS_NUM);
-        if (!PSRAM_IS_VALID(psram_id)) {
+        psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_QUAD_ID_BITS_NUM);
+        if (!PSRAM_QUAD_IS_VALID(psram_id)) {
             ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)psram_id);
             return ESP_ERR_NOT_SUPPORTED;
         }
     }
 
-    if (PSRAM_IS_64MBIT_TRIAL(psram_id)) {
+    if (PSRAM_QUAD_IS_64MBIT_TRIAL(psram_id)) {
         s_psram_size = PSRAM_SIZE_8MB;
     } else {
-        uint8_t density = PSRAM_SIZE_ID(psram_id);
-        const int eid = PSRAM_EID_BIT_47_40(psram_id);
+        uint8_t density = PSRAM_QUAD_SIZE_ID(psram_id);
+        const int eid = PSRAM_QUAD_EID_BIT_47_40(psram_id);
         s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB :
                        density == 0x1 ? PSRAM_SIZE_4MB :
                        density == 0x2 ? PSRAM_SIZE_8MB :
                        /* Do not use `density` for QEMU PSRAM since we don't want any future QSPI PSRAM
                         * that are 16MB or 32MB to be interpreted as QEMU PSRAM devices */
-                       eid == PSRAM_QEMU_16MB_ID ? PSRAM_SIZE_16MB :
-                       eid == PSRAM_QEMU_32MB_ID ? PSRAM_SIZE_32MB : 0;
+                       eid == PSRAM_QUAD_QEMU_16MB_ID ? PSRAM_SIZE_16MB :
+                       eid == PSRAM_QUAD_QEMU_32MB_ID ? PSRAM_SIZE_32MB : 0;
     }
 
     if ((s_psram_size == PSRAM_SIZE_8MB) && s_check_aps3204_2tmode()) {
@@ -306,10 +351,10 @@ esp_err_t esp_psram_impl_enable(void)
 static void config_psram_spi_phases(void)
 {
     psram_ctrlr_ll_set_read_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_HAL_CMD_QPI);
-    psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_QUAD_WRITE);
-    psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_FAST_READ_QUAD);
-    psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_ADDR_LENGTH);
-    psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_FAST_READ_QUAD_DUMMY);
+    psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CMD_LENGTH, PSRAM_QUAD_WRITE_QUAD);
+    psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CMD_LENGTH, PSRAM_QUAD_FAST_READ_QUAD);
+    psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_ADDR_LENGTH);
+    psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_FAST_READ_QUAD_DUMMY);
     psram_ctrlr_ll_set_cs_pin(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_CS_ID_1);
 }
 
@@ -330,16 +375,18 @@ esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
 
 /**
  * This function is to get the available physical psram size in bytes.
- *
- * When ECC is enabled, the available size will be reduced.
- * On S3 Quad PSRAM, ECC is not enabled for now.
+ * If ECC is enabled, available PSRAM size will be 7/8 times its physical size.
  */
 esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
 {
     if (!out_size_bytes) {
         return ESP_ERR_INVALID_ARG;
     }
 
+#if CONFIG_SPIRAM_ECC_ENABLE
+    *out_size_bytes = s_psram_size * 7 / 8;
+#else
     *out_size_bytes = s_psram_size;
+#endif
     return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
 }