refactor(hal): clean up some hal file dependency on sdkconfig.h

Author: suda-morris

components/esp_rom/esp32/include/esp32/rom/sha.h

@@ -27,15 +27,14 @@ typedef struct SHAContext {
     uint32_t total_input_bits[4];
 } SHA_CTX;
 
-enum SHA_TYPE {
+typedef enum SHA_TYPE {
     SHA1 = 0,
     SHA2_256,
     SHA2_384,
     SHA2_512,
 
-
     SHA_INVALID = -1,
-};
+} SHA_TYPE;
 
 /* Do not use these function in multi core mode due to
  * inside they have no safe implementation (without DPORT workaround).

components/hal/adc_hal.c

@@ -5,13 +5,12 @@
  */
 
 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "hal/adc_hal.h"
 #include "hal/assert.h"
 #include "soc/lldesc.h"
-#include "soc/soc_caps.h"
+#include "soc/soc_caps_full.h"
 
-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
 //ADC utilises I2S0 DMA on ESP32
 #include "hal/i2s_hal.h"
 #include "hal/i2s_types.h"
@@ -58,7 +57,7 @@ void adc_hal_digi_init(adc_hal_dma_ctx_t *hal)
     adc_ll_digi_set_clk_div(ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT);
 
     adc_ll_digi_dma_set_eof_num(hal->eof_num);
-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
     i2s_ll_rx_set_sample_bit(adc_hal_i2s_dev, SAMPLE_BITS, SAMPLE_BITS);
     i2s_ll_rx_enable_mono_mode(adc_hal_i2s_dev, 1);
     i2s_ll_rx_force_enable_fifo_mod(adc_hal_i2s_dev, 1);
@@ -91,20 +90,20 @@ void adc_hal_digi_deinit()
 ---------------------------------------------------------------*/
 static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t convert_mode)
 {
-#if CONFIG_IDF_TARGET_ESP32 || SOC_ADC_DIGI_CONTROLLER_NUM == 1
+#if SOC_IS(ESP32) || SOC_ADC_DIGI_CONTROLLER_NUM == 1
     return ADC_LL_DIGI_CONV_ONLY_ADC1;
 #elif (SOC_ADC_DIGI_CONTROLLER_NUM >= 2)
     switch (convert_mode) {
-        case ADC_CONV_SINGLE_UNIT_1:
-            return ADC_LL_DIGI_CONV_ONLY_ADC1;
-        case ADC_CONV_SINGLE_UNIT_2:
-            return ADC_LL_DIGI_CONV_ONLY_ADC2;
-        case ADC_CONV_BOTH_UNIT:
-            return ADC_LL_DIGI_CONV_BOTH_UNIT;
-        case ADC_CONV_ALTER_UNIT:
-            return ADC_LL_DIGI_CONV_ALTER_UNIT;
-        default:
-            abort();
+    case ADC_CONV_SINGLE_UNIT_1:
+        return ADC_LL_DIGI_CONV_ONLY_ADC1;
+    case ADC_CONV_SINGLE_UNIT_2:
+        return ADC_LL_DIGI_CONV_ONLY_ADC2;
+    case ADC_CONV_BOTH_UNIT:
+        return ADC_LL_DIGI_CONV_BOTH_UNIT;
+    case ADC_CONV_ALTER_UNIT:
+        return ADC_LL_DIGI_CONV_ALTER_UNIT;
+    default:
+        abort();
     }
 #endif
 }
@@ -118,7 +117,7 @@ static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t conve
  */
 static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuous_clk_src_t clk_src, uint32_t clk_src_freq_hz, uint32_t sample_freq_hz)
 {
-#if !CONFIG_IDF_TARGET_ESP32
+#if !SOC_IS(ESP32)
     uint32_t interval = clk_src_freq_hz / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / sample_freq_hz;
     //set sample interval
     adc_ll_digi_set_trigger_interval(interval);
@@ -218,14 +217,14 @@ void adc_hal_digi_dma_link(adc_hal_dma_ctx_t *hal, uint8_t *data_buf)
                 .dw0.suc_eof = 0,
                 .dw0.owner = 1,
                 .buffer = data_buf,
-                .next = &desc[n+1]
+                .next = &desc[n + 1]
             };
             eof_size -= this_len;
             data_buf += this_len;
             n++;
         }
     }
-    desc[n-1].next = desc_head;
+    desc[n - 1].next = desc_head;
 }
 
 adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len)

components/hal/apm_hal.c

@@ -5,12 +5,13 @@
  */
 
 #include <stdbool.h>
+#include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/apm_hal.h"
 #include "hal/apm_ll.h"
 #include "hal/log.h"
 
-#if CONFIG_IDF_TARGET_ESP32P4
+#if SOC_IS(ESP32P4)
 void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri,
                                      apm_ll_secure_mode_t sec_mode, bool enable)
 {
@@ -523,4 +524,4 @@ void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable)
     }
 }
 
-#endif //CONFIG_IDF_TARGET_ESP32P4
+#endif //SOC_IS(ESP32P4)

components/hal/emac_hal.c

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <string.h>
-#include "sdkconfig.h"
+#include "soc/soc_caps_full.h"
 #include "esp_attr.h"
 #include "hal/emac_hal.h"
 #include "hal/emac_ll.h"
@@ -29,7 +29,7 @@ void emac_hal_init(emac_hal_context_t *hal)
 {
     hal->dma_regs = &EMAC_DMA;
     hal->mac_regs = &EMAC_MAC;
-#if CONFIG_IDF_TARGET_ESP32
+#if SOC_IS(ESP32)
     hal->ext_regs = &EMAC_EXT;
 #else
     hal->ext_regs = NULL;
@@ -137,7 +137,7 @@ void emac_hal_init_dma_default(emac_hal_context_t *hal, emac_hal_dma_config_t *h
     /* DMAOMR Configuration */
     /* Enable Dropping of TCP/IP Checksum Error Frames */
     emac_ll_drop_tcp_err_frame_enable(hal->dma_regs, true);
-#if CONFIG_IDF_TARGET_ESP32P4
+#if SOC_IS(ESP32P4)
     /* Disable Receive Store Forward (Rx FIFO is only 256B) */
     emac_ll_recv_store_forward_enable(hal->dma_regs, false);
 #else

components/hal/esp32/efuse_hal.c

@@ -1,15 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "sdkconfig.h"
 #include <sys/param.h>
-#include "soc/soc_caps.h"
 #include "hal/efuse_ll.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
+#include "hal/config.h"
 #include "soc/syscon_reg.h"
 #include "esp_attr.h"
 
@@ -30,11 +29,11 @@ IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
     case 3:
         chip_ver = 2;
         break;
-#if CONFIG_IDF_ENV_FPGA
+#if HAL_CONFIG_EFUSE_ENV_FPGA
     case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */
         chip_ver = 3;
         break;
-#endif // CONFIG_IDF_ENV_FPGA
+#endif // HAL_CONFIG_EFUSE_ENV_FPGA
     case 7:
         chip_ver = 3;
         break;

components/hal/esp32c2/clk_tree_hal.c

@@ -4,9 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "sdkconfig.h"
 #include "soc/clkout_channel.h"
 #include "hal/assert.h"
+#include "hal/config.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/gpio_ll.h"
@@ -78,8 +78,8 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
 {
     uint32_t freq = clk_ll_xtal_load_freq_mhz();
     if (freq == 0) {
-        HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_XTAL_FREQ);
-        return CONFIG_XTAL_FREQ;
+        HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", HAL_CONFIG_XTAL_HINT_FREQ_MHZ);
+        return HAL_CONFIG_XTAL_HINT_FREQ_MHZ;
     }
     return freq;
 }

components/hal/esp32c5/efuse_hal.c

@@ -5,7 +5,6 @@
  */
 
 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"

components/hal/esp32c6/efuse_hal.c

@@ -5,7 +5,6 @@
  */
 
 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"

components/hal/esp32c61/efuse_hal.c

@@ -5,7 +5,6 @@
  */
 
 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"

components/hal/esp32h2/efuse_hal.c

@@ -5,7 +5,6 @@
  */
 
 #include <sys/param.h>
-#include "sdkconfig.h"
 #include "soc/soc_caps.h"
 #include "soc/chip_revision.h"
 #include "hal/assert.h"