refactor(xtensa): Rename specreg.h register macros

This commit renames all registers in xtensa/specreg.h to by adding the
prefix XT_REG_. This is done to avoid naming collisions with similar
variable names. A new register file, viz., xt_specreg.h is created. The
previous names are still available to use but have been deprecated.

Closes #12723
Merges #16040

Author: nebkat

components/bootloader_support/src/esp32/bootloader_esp32.c

@@ -167,7 +167,7 @@ esp_err_t bootloader_init(void)
 
 #if XCHAL_ERRATUM_572
     uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
-    WSR(MEMCTL, memctl);
+    WSR(XT_REG_MEMCTL, memctl);
 #endif // XCHAL_ERRATUM_572
 
 // In RAM_APP, memory will be initialized in `call_start_cpu0`

components/bootloader_support/src/esp32s3/bootloader_esp32s3.c

@@ -144,7 +144,7 @@ esp_err_t bootloader_init(void)
 
 #if XCHAL_ERRATUM_572
     uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
-    WSR(MEMCTL, memctl);
+    WSR(XT_REG_MEMCTL, memctl);
 #endif // XCHAL_ERRATUM_572
 
     bootloader_ana_reset_config();

components/bt/controller/esp32/hli_vectors.S

@@ -57,17 +57,17 @@ xt_highint4:
     wsr     a0, CCOMPARE2
 
     /* Enable Timer 2 interrupt */
-    rsr     a0, INTENABLE
+    rsr     a0, XT_REG_INTENABLE
     extui   a0, a0, 16, 1
     bnez    a0, 1f
     movi    a0, 0
-    xsr     a0, INTENABLE     /* disable all interrupts */
+    xsr     a0, XT_REG_INTENABLE     /* disable all interrupts */
     /* And a0 with (1 << 16) for Timer 2 interrupt mask */
     addmi   a0, a0, (1<<14)
     addmi   a0, a0, (1<<14)
     addmi   a0, a0, (1<<14)
     addmi   a0, a0, (1<<14)
-    wsr     a0, INTENABLE    /* Enable Timer 2 */
+    wsr     a0, XT_REG_INTENABLE    /* Enable Timer 2 */
 1:
 #endif
 
@@ -76,37 +76,37 @@ xt_highint4:
     s32i    a1, a0, 4
     s32i    a2, a0, 8
     s32i    a3, a0, 12
-    rsr     a2, EXCSAVE_4  /* holds the value of a0 */
+    rsr     a2, XT_REG_EXCSAVE_4  /* holds the value of a0 */
     s32i    a2, a0, 0
 
     /* Save special registers */
     addi    a0, a0, SPECREG_OFFSET
-    rsr     a2, WINDOWBASE
+    rsr     a2, XT_REG_WINDOWBASE
     s32i    a2, a0, 0
-    rsr     a2, WINDOWSTART
+    rsr     a2, XT_REG_WINDOWSTART
     s32i    a2, a0, 4
-    rsr     a2, SAR
+    rsr     a2, XT_REG_SAR
     s32i    a2, a0, 8
-    rsr     a2, LBEG
+    rsr     a2, XT_REG_LBEG
     s32i    a2, a0, 12
-    rsr     a2, LEND
+    rsr     a2, XT_REG_LEND
     s32i    a2, a0, 16
-    rsr     a2, LCOUNT
+    rsr     a2, XT_REG_LCOUNT
     s32i    a2, a0, 20
     rsr     a2, EPC1
     s32i    a2, a0, 24
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
     movi    a0, 0
-    xsr     a0, INTENABLE     /* disable all interrupts */
+    xsr     a0, XT_REG_INTENABLE     /* disable all interrupts */
     movi    a2, ~(1<<16)
     and     a0, a2, a0
-    wsr     a0, INTENABLE
+    wsr     a0, XT_REG_INTENABLE
 #endif
 
     /* disable exception mode, window overflow */
     movi    a0, PS_INTLEVEL(5) | PS_EXCM
-    wsr     a0, PS
+    wsr     a0, XT_REG_PS
     rsync
 
     /* Save the remaining physical registers.
@@ -153,12 +153,12 @@ xt_highint4:
     /* a0 still points to _l4_save_ctx */
 
     /* Can clear WINDOWSTART now, all registers are saved */
-    rsr     a2, WINDOWBASE
+    rsr     a2, XT_REG_WINDOWBASE
     /* WINDOWSTART = (1 << WINDOWBASE) */
     movi    a3, 1
     ssl     a2
     sll     a3, a3
-    wsr     a3, WINDOWSTART
+    wsr     a3, XT_REG_WINDOWSTART
 
 _highint4_stack_switch:
     movi    a0, 0
@@ -169,7 +169,7 @@ _highint4_stack_switch:
 
     /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
     movi    a6, PS_INTLEVEL(4) | PS_UM | PS_WOE
-    wsr     a6, PS
+    wsr     a6, XT_REG_PS
     rsync
 
     /* Call C handler */
@@ -180,21 +180,21 @@ _highint4_stack_switch:
 
     /* Done with C handler; re-enable exception mode, disabling window overflow */
     movi    a2, PS_INTLEVEL(5) | PS_EXCM    /* TOCHECK */
-    wsr     a2, PS
+    wsr     a2, XT_REG_PS
     rsync
 
     /* Restore the special registers.
      * WINDOWSTART will be restored near the end.
      */
     movi    a0, _l4_save_ctx + SPECREG_OFFSET
     l32i    a2, a0, 8
-    wsr     a2, SAR
+    wsr     a2, XT_REG_SAR
     l32i    a2, a0, 12
-    wsr     a2, LBEG
+    wsr     a2, XT_REG_LBEG
     l32i    a2, a0, 16
-    wsr     a2, LEND
+    wsr     a2, XT_REG_LEND
     l32i    a2, a0, 20
-    wsr     a2, LCOUNT
+    wsr     a2, XT_REG_LCOUNT
     l32i    a2, a0, 24
     wsr     a2, EPC1
 
@@ -247,12 +247,12 @@ _highint4_stack_switch:
     movi    a0, _l4_save_ctx
 
     l32i    a2, a0, SPECREG_OFFSET + 4
-    wsr     a2, WINDOWSTART
+    wsr     a2, XT_REG_WINDOWSTART
 
     l32i    a1, a0, 4
     l32i    a2, a0, 8
     l32i    a3, a0, 12
-    rsr     a0, EXCSAVE_4  /* holds the value of a0 before the interrupt handler */
+    rsr     a0, XT_REG_EXCSAVE_4  /* holds the value of a0 before the interrupt handler */
 
     /* Return from the interrupt, restoring PS from EPS_4 */
     rfi     4

components/esp_gdbstub/src/port/xtensa/gdbstub-entry.S

@@ -24,9 +24,9 @@ esp_gdbstub_int:
     #if XCHAL_HAVE_WINDOWED
     s32e    a0, sp, -12                     /* for debug backtrace */
     #endif
-    rsr     a0, PS                          /* save interruptee's PS */
+    rsr     a0, XT_REG_PS                   /* save interruptee's PS */
     s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_1                       /* save interruptee's PC */
+    rsr     a0, XT_REG_EPC_1                /* save interruptee's PC */
     s32i    a0, sp, XT_STK_PC
     #if XCHAL_HAVE_WINDOWED
     s32e    a0, sp, -16                     /* for debug backtrace */
@@ -35,21 +35,21 @@ esp_gdbstub_int:
     s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
 
     /* Save exc cause and vaddr into exception frame */
-    rsr     a0, EXCCAUSE
+    rsr     a0, XT_REG_EXCCAUSE
     s32i    a0, sp, XT_STK_EXCCAUSE
-    rsr     a0, EXCVADDR
+    rsr     a0, XT_REG_EXCVADDR
     s32i    a0, sp, XT_STK_EXCVADDR
 
 
     /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
-    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    rsr     a0, XT_REG_EXCSAVE_1            /* save interruptee's a0 */
 
     s32i    a0, sp, XT_STK_A0
 
     /* Save context pointer as input parameter */
     rsr  a6, excsave1
 
-    rsr     a3, EPS
+    rsr     a3, XT_REG_EPS
     s32i    a3, sp, XT_STK_PS   // store PS to the ps place
     movi    a3, gdbstub_handle_uart_int
     callx0  a3

components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c

@@ -7,7 +7,7 @@
 #include <string.h>
 #include "esp_gdbstub_common.h"
 #include "soc/soc_memory_layout.h"
-#include "xtensa/config/specreg.h"
+#include "xtensa/config/xt_specreg.h"
 #include "sdkconfig.h"
 #include "esp_cpu.h"
 #include "esp_ipc_isr.h"
@@ -35,8 +35,8 @@ static void update_regfile_common(esp_gdbstub_gdb_regfile_t *dst)
     }
     dst->windowbase = 0;
     dst->windowstart = 0x1;
-    RSR(CONFIGID0, dst->configid0);
-    RSR(CONFIGID1, dst->configid1);
+    RSR(XT_REG_CONFIGID0, dst->configid0);
+    RSR(XT_REG_CONFIGID1, dst->configid1);
 }
 
 #if XCHAL_HAVE_FP
@@ -111,7 +111,7 @@ void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_
     current_tcb_ptr = pxCurrentTCBs[esp_cpu_get_core_id()];
 #endif
     uint32_t cp_enabled;
-    RSR(CPENABLE, cp_enabled);
+    RSR(XT_REG_CPENABLE, cp_enabled);
 
     // Check if the co-processor is enabled
     if (cp_enabled) {
@@ -182,7 +182,7 @@ void esp_gdbstub_tcb_frame_to_regfile(dummy_tcb_t *tcb, esp_gdbstub_gdb_regfile_
 #endif
 
     uint32_t cp_enabled;
-    RSR(CPENABLE, cp_enabled);
+    RSR(XT_REG_CPENABLE, cp_enabled);
 
     void *current_tcb_ptr = tcb;
     uint32_t *current_fpu_ptr = NULL;
@@ -309,8 +309,8 @@ void esp_gdbstub_stall_other_cpus_end(void)
  * */
 void esp_gdbstub_clear_step(void)
 {
-    WSR(ICOUNT, 0);
-    WSR(ICOUNTLEVEL, 0);
+    WSR(XT_REG_ICOUNT, 0);
+    WSR(XT_REG_ICOUNTLEVEL, 0);
 }
 
 /** @brief GDB do step
@@ -326,8 +326,8 @@ void esp_gdbstub_do_step( esp_gdbstub_frame_t *frame)
     level &= 0x7;
     level += 1;
 
-    WSR(ICOUNTLEVEL, level);
-    WSR(ICOUNT, -2);
+    WSR(XT_REG_ICOUNTLEVEL, level);
+    WSR(XT_REG_ICOUNT, -2);
 }
 
 /** @brief GDB trigger other CPU
@@ -364,7 +364,7 @@ void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, ui
 #if XCHAL_HAVE_FP
     void  *ptr1;
     uint32_t cp_enabled;
-    RSR(CPENABLE, cp_enabled);
+    RSR(XT_REG_CPENABLE, cp_enabled);
     if (cp_enabled != 0) {
         if (reg_index == 87) {
             asm volatile ("lsi f0, %0, 0" :: "a" (ptr0));

components/esp_gdbstub/src/port/xtensa/xt_debugexception.S

@@ -22,9 +22,9 @@ _xt_panic_gdbstub:
     s32i    a0, sp, XT_STK_EXIT
     s32i    a0, sp, XT_STK_A0
 
-    rsr     a0, PS                          /* save interruptee's PS */
+    rsr     a0, XT_REG_PS                   /* save interruptee's PS */
     s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_1                       /* save interruptee's PC */
+    rsr     a0, XT_REG_EPC_1                /* save interruptee's PC */
     s32i    a0, sp, XT_STK_PC
     call0   _xt_context_save                /* Save full context*/
     addi     a7, sp, XT_STK_FRMSZ
@@ -33,29 +33,29 @@ _xt_panic_gdbstub:
     s32i    a13, sp, XT_STK_A13
 
     /* Save exc cause and vaddr into exception frame */
-    rsr     a0, EXCCAUSE
+    rsr     a0, XT_REG_EXCCAUSE
     s32i    a0, sp, XT_STK_EXCCAUSE
-    rsr     a0, EXCVADDR
+    rsr     a0, XT_REG_EXCVADDR
     s32i    a0, sp, XT_STK_EXCVADDR
 
     /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
-    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    rsr     a0, XT_REG_EXCSAVE_1            /* save interruptee's a0 */
 
     /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
     movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
-    wsr     a0, PS
+    wsr     a0, XT_REG_PS
 
     //Call gdbstub handler
 
-    rsr     a0,(EPC + XCHAL_DEBUGLEVEL)
+    rsr     a0,(XT_REG_EPC + XCHAL_DEBUGLEVEL)
     s32i    a0, sp, XT_STK_PC
     mov     a6, sp
-    rsr     a9, EPS_6
+    rsr     a9, XT_REG_EPS_6
     s32i    a9, sp, XT_STK_PS   // store PS to the ps place
     movi    a11, gdbstub_handle_debug_int
     callx4  a11                          /* Call interrupt handler */
     l32i    a0, sp, XT_STK_PC
-    wsr     a0,(EPC + XCHAL_DEBUGLEVEL)
+    wsr     a0,(XT_REG_EPC + XCHAL_DEBUGLEVEL)
     call0   _xt_context_restore         /* Restore full context*/
     l32i    a12, sp, XT_STK_A12
     l32i    a13, sp, XT_STK_A13

components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c

@@ -307,11 +307,11 @@ TEST_CASE("test for DPORT access performance", "[esp32]")
 static uint32_t start, end;
 
 #define BENCHMARK_START() do {                                      \
-        RSR(CCOUNT, start);                                         \
+        RSR(XT_REG_CCOUNT, start);                                         \
     } while(0)
 
 #define BENCHMARK_END(OPERATION) do {                               \
-        RSR(CCOUNT, end);                                           \
+        RSR(XT_REG_CCOUNT, end);                                           \
         printf("%s took %"PRIu32" cycles/op (%"PRIu32" cycles for %d ops)\n",     \
                OPERATION, (end - start)/REPEAT_OPS,                 \
                (end - start), REPEAT_OPS);                          \

components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S

@@ -40,7 +40,7 @@ xt_highint5:
     wsr a0, CCOMPARE2
     esync
 
-    rsr     a0, EXCSAVE_5 // restore a0
+    rsr     a0, XT_REG_EXCSAVE_5 // restore a0
     rfi     5
 
 
@@ -74,7 +74,7 @@ xt_highint5:
     l32i    a4, a0, L5_INTR_A4_OFFSET
     rsync
 .L_xt_highint5_exit:
-    rsr     a0, EXCSAVE_5                   // restore a0
+    rsr     a0, XT_REG_EXCSAVE_5                   // restore a0
     rfi     5
 
 /* The linker has no reason to link in this file; all symbols it exports are already defined

components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c

@@ -215,13 +215,13 @@ float IRAM_ATTR test_fp_benchmark_fp_divide(int counts, unsigned *cycles)
 {
     float f = MAXFLOAT;
     uint32_t before, after;
-    RSR(CCOUNT, before);
+    RSR(XT_REG_CCOUNT, before);
 
     for (int i = 0; i < counts; i++) {
         f /= 1.000432f;
     }
 
-    RSR(CCOUNT, after);
+    RSR(XT_REG_CCOUNT, after);
     *cycles = (after - before) / counts;
 
     return f;
@@ -254,13 +254,13 @@ float IRAM_ATTR test_fp_benchmark_fp_sqrt(int counts, unsigned *cycles)
 {
     float f = MAXFLOAT;
     uint32_t before, after;
-    RSR(CCOUNT, before);
+    RSR(XT_REG_CCOUNT, before);
 
     for (int i = 0; i < counts; i++) {
         f = sqrtf(f);
     }
 
-    RSR(CCOUNT, after);
+    RSR(XT_REG_CCOUNT, after);
     *cycles = (after - before) / counts;
 
     return f;