Merge branch 'refactor/split_esp32s2_soc_include_folder' into 'master'

refactor(soc): sort esp32s2 soc headers

See merge request espressif/esp-idf!33310

Author: L-KAYA

components/soc/esp32s2/include/soc/dport_reg.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,15 +10,15 @@
 extern "C" {
 #endif
 
-#include "interrupt_reg.h"
-#include "system_reg.h"
-#include "sensitive_reg.h"
-#include "soc.h"
+#include "soc/interrupt_reg.h"
+#include "soc/system_reg.h"
+#include "soc/sensitive_reg.h"
+#include "soc/soc.h"
 
 #define DPORT_DATE_REG SYSTEM_DATE_REG
 
 #ifndef __ASSEMBLER__
-#include "dport_access.h"
+#include "soc/dport_access.h"
 #endif
 
 #ifdef __cplusplus

components/soc/esp32s2/include/soc/soc.h

@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 

components/soc/esp32s2/include/soc/usb_dwc_struct.h

@@ -33,7 +33,7 @@ typedef union {
         uint32_t hnpreq: 1;
         uint32_t hstsethnpen: 1;
         uint32_t devhnpen: 1;
-        uint32_t ehen: 1;
+        uint32_t ehen: 1;       // codespell:ignore ehen
         uint32_t reserved_13: 2;
         uint32_t dbncefltrbypass: 1;
         uint32_t conidsts: 1;

components/soc/esp32s2/register/soc/.gitkeep

@@ -11,7 +11,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x000)
 /* APB_CTRL_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
 /*description: */

components/soc/esp32s2/include/soc/apb_ctrl_reg.h renamed to components/soc/esp32s2/register/soc/apb_ctrl_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_APB_SARADC_REG_H_
 #define _SOC_APB_SARADC_REG_H_
 
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
+#include "soc/soc.h"
 #define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x000)
 /* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
 /*description: wait arbit signal stable after sar_done*/

components/soc/esp32s2/include/soc/apb_ctrl_struct.h renamed to components/soc/esp32s2/register/soc/apb_ctrl_struct.h

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #define ASSIST_DEBUG_BASE DR_REG_ASSIST_DEBUG_BASE
 
 #define ASSIST_DEBUG_INTERRUPT_ENA              ((ASSIST_DEBUG_BASE) +0x00)
@@ -80,8 +85,8 @@
 
 #define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS	((ASSIST_DEBUG_BASE) +0x64)
 /* register layout:
- * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
- * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
+ * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for possible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
+ * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for possible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
 */
 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M             ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V             0x3F

components/soc/esp32s2/include/soc/apb_saradc_reg.h renamed to components/soc/esp32s2/register/soc/apb_saradc_reg.h

@@ -573,7 +573,7 @@ extern "C" {
 #define CP_DMA_CRC_CAL_EN_V  0x00000001
 #define CP_DMA_CRC_CAL_EN_S  9
 /** CP_DMA_CRC_BIG_ENDIAN_EN : R/W; bitpos: [10]; default: 0;
- *  Set this bit to reorder the bit of data which will be send to excute crc.
+ *  Set this bit to reorder the bit of data which will be send to execute crc.
  */
 #define CP_DMA_CRC_BIG_ENDIAN_EN    (BIT(10))
 #define CP_DMA_CRC_BIG_ENDIAN_EN_M  (CP_DMA_CRC_BIG_ENDIAN_EN_V << CP_DMA_CRC_BIG_ENDIAN_EN_S)
@@ -629,7 +629,7 @@ extern "C" {
 #define CP_DMA_FIFO_EMPTY_S  23
 
 /** CP_DMA_OUT_ST_REG register
- *  Status register of trasmitting data
+ *  Status register of transmitting data
  */
 #define CP_DMA_OUT_ST_REG (DR_REG_CP_BASE + 0x44)
 /** CP_DMA_OUTLINK_DSCR_ADDR : RO; bitpos: [17:0]; default: 0;